Serial port support for ATMega1280 (contributed by Fabio Bizzi).

[bertos.git] / bertos / cpu / cortex-m3 / drv / clock_lm3s.c

diff --git a/bertos/cpu/cortex-m3/drv/clock_lm3s.c b/bertos/cpu/cortex-m3/drv/clock_lm3s.c
index 8790b0e6ed69319fcdbf3f644a2417f0d199811a..df4681ea3ef860b9c62d5cce8713c07c8722cb2c 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/clock_lm3s.c
+++ b/bertos/cpu/cortex-m3/drv/clock_lm3s.c
@@ -35,10 +35,13 @@
  * \author Andrea Righi <arighi@develer.com>
  */
 
+#include "clock_lm3s.h"
+
 #include <cfg/compiler.h>
 #include <cfg/debug.h>
-#include "io/lm3s.h"
-#include "clock_lm3s.h"
+
+#include <io/lm3s.h>
+
 
 /* The PLL VCO frequency is 400 MHz */
 #define PLL_VCO        400000000UL
@@ -51,15 +54,18 @@
 /*
  * Very small delay: each loop takes 3 cycles.
  */
-INLINE void __delay(unsigned long iterations)
+void NAKED lm3s_busyWait(unsigned long iterations)
 {
+       register uint32_t __n asm("r0") = iterations;
+
        asm volatile (
-               "1:     subs    %0, #1\n\t"
-               "       bne 1b\n\t"
-               : "=r"(iterations) : : "memory", "cc");
+               "1: subs r0, #1\n\t"
+               "bne 1b\n\t"
+               "bx lr\n\t"
+               : : "r"(__n) : "memory", "cc");
 }
 
-unsigned long clock_get_rate(void)
+INLINE unsigned long clock_get_rate(void)
 {
        reg32_t rcc = HWREG(SYSCTL_RCC);
 
@@ -85,7 +91,7 @@ INLINE int evaluate_sysdiv(unsigned long freq)
        return i;
 }
 
-void clock_set_rate(void)
+void clock_init(void)
 {
        reg32_t rcc, rcc2;
        unsigned long clk;
@@ -110,6 +116,8 @@ void clock_set_rate(void)
        HWREG(SYSCTL_RCC) = rcc;
        HWREG(SYSCTL_RCC) = rcc2;
 
+       lm3s_busyWait(16);
+
        /*
         * Step #2: select the crystal value (XTAL) and oscillator source
         * (OSCSRC), and clear the PWRDN bit in RCC/RCC2. Setting the XTAL
@@ -134,7 +142,7 @@ void clock_set_rate(void)
         HWREG(SYSCTL_RCC) = rcc;
        HWREG(SYSCTL_RCC) = rcc2;
 
-       __delay(16);
+       lm3s_busyWait(16);
 
        /*
         * Step #3: select the desired system divider (SYSDIV) in RCC/RCC2 and
@@ -166,5 +174,5 @@ void clock_set_rate(void)
 
        HWREG(SYSCTL_RCC) = rcc;
 
-       __delay(16);
+       lm3s_busyWait(16);
 }