*
* -->
*
- * \brief AT91SAM3 clocking driver.
+ * \brief ATSAM3 clock setup.
*
* \author Stefano Fedrigo <aleph@develer.com>
*/
#include "clock_sam3.h"
+#include <io/sam3_pmc.h>
+#include <io/sam3_sysctl.h>
+#include <cfg/compiler.h>
+#include <cfg/macros.h>
+
+
+/* Frequency of board main oscillator */
+#define BOARDOSC_FREQ 12000000
+
+/* Main crystal oscillator startup time, optimal value for CPU_FREQ == 48 MHz */
+#define BOARD_OSC_COUNT (CKGR_MOR_MOSCXTST(0x8))
+
+/* Timer countdown timeout for clock initialization operations */
+#define CLOCK_TIMEOUT 0xFFFFFFFF
+
+
+/*
+ * Try to evaluate the correct divider and multiplier value depending
+ * on the desired CPU frequency.
+ *
+ * We try all combinations in a certain range of divider and multiplier
+ * values. The range can change, with better match with "strange"
+ * frequencies, but boot time will be longer.
+ *
+ * Limits for SAM3N: divider [1,255], multiplier [1,2047].
+ */
+INLINE uint32_t evaluate_pll(void)
+{
+ int mul, div, best_mul, best_div;
+ int best_delta = CPU_FREQ;
+ int freq = 0;
+
+ for (mul = 1; mul <= 8; mul++)
+ {
+ for (div = 1; div <= 24; div++)
+ {
+ freq = BOARDOSC_FREQ / div * (1 + mul);
+ if (ABS((int)CPU_FREQ - freq) < best_delta) {
+ best_delta = ABS((int)CPU_FREQ - freq);
+ best_mul = mul;
+ best_div = div;
+ }
+ }
+ }
+
+ // Bit 29 must always be set to 1
+ return CKGR_PLLR_DIV(best_div) | CKGR_PLLR_MUL(best_mul) | BV(29);
+}
+
void clock_init(void)
{
+ uint32_t timeout;
+
+ // Select external slow clock
+ if (!(SUPC_SR_R & SUPC_SR_OSCSEL))
+ {
+ SUPC_CR_R = SUPC_CR_XTALSEL | SUPC_CR_KEY(0xA5);
+ while (!(SUPC_SR_R & SUPC_SR_OSCSEL));
+ }
+
+ // Initialize main oscillator
+ if (!(CKGR_MOR_R & CKGR_MOR_MOSCSEL))
+ {
+ CKGR_MOR_R = CKGR_MOR_KEY(0x37) | BOARD_OSC_COUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN;
+ timeout = CLOCK_TIMEOUT;
+ while (!(PMC_SR_R & PMC_SR_MOSCXTS) && --timeout);
+ }
+
+ // Switch to external oscillator
+ CKGR_MOR_R = CKGR_MOR_KEY(0x37) | BOARD_OSC_COUNT | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL;
+ timeout = CLOCK_TIMEOUT;
+ while (!(PMC_SR_R & PMC_SR_MOSCSELS) && --timeout);
+
+ PMC_MCKR_R = (PMC_MCKR_R & ~(uint32_t)PMC_MCKR_CSS_M) | PMC_MCKR_CSS_MAIN_CLK;
+ timeout = CLOCK_TIMEOUT;
+ while (!(PMC_SR_R & PMC_SR_MCKRDY) && --timeout);
+
+ // Initialize and enable PLL clock
+ CKGR_PLLR_R = evaluate_pll() | CKGR_PLLR_STUCKTO1 | CKGR_PLLR_PLLCOUNT(0x1);
+ timeout = CLOCK_TIMEOUT;
+ while (!(PMC_SR_R & PMC_SR_LOCK) && --timeout);
+
+ PMC_MCKR_R = PMC_MCKR_CSS_MAIN_CLK;
+ timeout = CLOCK_TIMEOUT;
+ while (!(PMC_SR_R & PMC_SR_MCKRDY) && --timeout);
+
+ PMC_MCKR_R = PMC_MCKR_CSS_PLL_CLK;
+ timeout = CLOCK_TIMEOUT;
+ while (!(PMC_SR_R & PMC_SR_MCKRDY) && --timeout);
}