Remove duplicate define. Put all phy chip specific defines in its

[bertos.git] / bertos / cpu / cortex-m3 / drv / clock_sam3.c

diff --git a/bertos/cpu/cortex-m3/drv/clock_sam3.c b/bertos/cpu/cortex-m3/drv/clock_sam3.c
index fbc79062216a4ad8207e23423412e65a1aa91860..fcb46c4b29dd06c5454eebf8ad05366e10848abb 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/clock_sam3.c
+++ b/bertos/cpu/cortex-m3/drv/clock_sam3.c
@@ -30,28 +30,43 @@
  *
  * -->
  *
- * \brief AT91SAM3 clocking driver.
+ * \brief Atmel SAM3 clock setup.
  *
  * \author Stefano Fedrigo <aleph@develer.com>
  */
 
 #include "clock_sam3.h"
-#include <io/sam3_pmc.h>
 #include <cfg/compiler.h>
 #include <cfg/macros.h>
+#include <io/sam3.h>
 
-/* Value to use when writing CKGR_MOR, to unlock write */
-#define CKGR_KEY  0x37
+
+/* Frequency of board main oscillator */
+#define BOARDOSC_FREQ  12000000
+
+/* Timer countdown timeout for clock initialization operations */
+#define CLOCK_TIMEOUT    0xFFFFFFFF
+
+
+#if CPU_FREQ == 84000000 || CPU_FREQ == 48000000
+
+INLINE uint32_t evaluate_pll(void)
+{
+       return CKGR_PLLR_MUL(CPU_FREQ / BOARDOSC_FREQ * 2 - 1) | CKGR_PLLR_DIV(2);
+}
+
+#else
+
+#warning CPU clock frequency non-standard setting: multiplier and divider values \
+ will be computed at runtime: effective computed frequency could be different \
+ from expected.
 
 /*
  * Try to evaluate the correct divider and multiplier value depending
  * on the desired CPU frequency.
  *
  * We try all combinations in a certain range of divider and multiplier
- * values.  The range can change, with better match with "strange"
- * frequencies, but boot time will be longer.
- *
- * Limits for SAM3N: divider [1,255], multiplier [1,2047].
+ * values.  Start with higher multipliers and divisors, generally better.
  */
 INLINE uint32_t evaluate_pll(void)
 {
@@ -59,12 +74,11 @@ INLINE uint32_t evaluate_pll(void)
        int best_delta = CPU_FREQ;
        int freq = 0;
 
-       for (mul = 1; mul <= 8; mul++)
+       for (mul = 13; mul > 0; mul--)
        {
-               for (div = 1; div <= 24; div++)
+               for (div = 24; div > 0; div--)
                {
-                       // RC oscillator set to 12 MHz
-                       freq = 12000000 / div * (1 + mul);
+                       freq = BOARDOSC_FREQ / div * (1 + mul);
                        if (ABS((int)CPU_FREQ - freq) < best_delta) {
                                best_delta = ABS((int)CPU_FREQ - freq);
                                best_mul = mul;
@@ -73,21 +87,60 @@ INLINE uint32_t evaluate_pll(void)
                }
        }
 
-       // Bit 29 must always be set to 1
-       return CKGR_PLLR_DIV(best_div) | CKGR_PLLR_MUL(best_mul) | BV(29);
+       return CKGR_PLLR_DIV(best_div) | CKGR_PLLR_MUL(best_mul);
 }
 
+#endif /* CPU_FREQ */
 
 void clock_init(void)
 {
-       /* Enable and configure internal Fast RC oscillator */
-       CKGR_MOR_R =
-               CKGR_MOR_KEY(CKGR_KEY)       // Unlock key
-               | CKGR_MOR_MOSCRCEN          // Main On-Chip RC oscillator enable
-               | CKGR_MOR_MOSCRCF_12MHZ;    // RC oscillator frequency
+       uint32_t timeout;
+
+       /* Disable watchdog */
+       WDT_MR = BV(WDT_WDDIS);
+
+       /* Set wait states for flash access, needed for higher CPU clock rates */
+       EEFC0_FMR = EEFC_FMR_FWS(3);
+#ifdef EEFC1_FMR
+       EEFC1_FMR = EEFC_FMR_FWS(3);
+#endif
+
+       // Initialize main oscillator
+       if (!(CKGR_MOR & BV(CKGR_MOR_MOSCSEL)))
+       {
+               CKGR_MOR = CKGR_MOR_KEY(0x37) | CKGR_MOR_MOSCXTST(0x8)
+                       | BV(CKGR_MOR_MOSCRCEN) | BV(CKGR_MOR_MOSCXTEN);
+               timeout = CLOCK_TIMEOUT;
+               while (!(PMC_SR & BV(PMC_SR_MOSCXTS)) && --timeout);
+       }
+
+       // Switch to external oscillator
+       CKGR_MOR = CKGR_MOR_KEY(0x37) | CKGR_MOR_MOSCXTST(0x8)
+               | BV(CKGR_MOR_MOSCRCEN) | BV(CKGR_MOR_MOSCXTEN) | BV(CKGR_MOR_MOSCSEL);
+       timeout = CLOCK_TIMEOUT;
+       while (!(PMC_SR & BV(PMC_SR_MOSCXTS)) && --timeout);
+
+       // Initialize and enable PLL clock
+       CKGR_PLLR = evaluate_pll() | BV(CKGR_PLLR_STUCKTO1) | CKGR_PLLR_PLLCOUNT(0x2);
+       timeout = CLOCK_TIMEOUT;
+       while (!(PMC_SR & BV(PMC_SR_LOCK)) && --timeout);
+
+       PMC_MCKR = PMC_MCKR_CSS_MAIN_CLK;
+       timeout = CLOCK_TIMEOUT;
+       while (!(PMC_SR & BV(PMC_SR_MCKRDY)) && --timeout);
 
-       /* Master clock: select PLL clock and no prescaling */
-       PMC_MCKR_R = PMC_MCKR_CSS_PLL_CLK;
+       PMC_MCKR = PMC_MCKR_CSS_PLL_CLK;
+       timeout = CLOCK_TIMEOUT;
+       while (!(PMC_SR & BV(PMC_SR_MCKRDY)) && --timeout);
 
-       CKGR_PLLR_R = evaluate_pll();
+       /* Enable clock on PIO for inputs */
+       // TODO: move this in gpio_init() for better power management?
+       pmc_periphEnable(PIOA_ID);
+       pmc_periphEnable(PIOB_ID);
+       pmc_periphEnable(PIOC_ID);
+#ifdef PIOF_ID
+       pmc_periphEnable(PIOD_ID);
+       pmc_periphEnable(PIOE_ID);
+       pmc_periphEnable(PIOF_ID);
+#endif
 }