Reorder includes.

[bertos.git] / bertos / cpu / cortex-m3 / drv / clock_stm32.c

diff --git a/bertos/cpu/cortex-m3/drv/clock_stm32.c b/bertos/cpu/cortex-m3/drv/clock_stm32.c
index cd8e0f4286d708a0c377b6a5696b23e62fe589a7..c1db8b6b1d18621fbbc688059930f2dcc190be04 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/clock_stm32.c
+++ b/bertos/cpu/cortex-m3/drv/clock_stm32.c
@@ -35,10 +35,12 @@
  * \author Andrea Righi <arighi@develer.com>
  */
 
+#include "clock_stm32.h"
+
 #include <cfg/compiler.h>
 #include <cfg/debug.h>
+
 #include <io/stm32.h>
-#include "clock_stm32.h"
 
 struct RCC *RCC;
 
@@ -66,7 +68,7 @@ INLINE int rcc_get_flag_status(uint32_t flag)
 
 INLINE uint16_t pll_clock(void)
 {
-       int div, mul;
+       unsigned int div, mul;
 
        /* Hopefully this is evaluate at compile time... */
        for (div = 2; div; div--)
@@ -126,8 +128,23 @@ void clock_init(void)
        rcc_pll_config();
        while(!rcc_get_flag_status(RCC_FLAG_PLLRDY));
 
+       /* Configure USB clock (48MHz) */
+       *CFGR_USBPRE_BB = RCC_USBCLK_PLLCLK_1DIV5;
+       /* Configure ADC clock: PCLK2 (9MHz) */
+       RCC->CFGR &= CFGR_ADCPRE_RESET_MASK;
+       RCC->CFGR |= RCC_PCLK2_DIV8;
+       /* Configure system clock dividers: PCLK2 (72MHz) */
+       RCC->CFGR &= CFGR_PPRE2_RESET_MASK;
+       RCC->CFGR |= RCC_HCLK_DIV1 << 3;
+       /* Configure system clock dividers: PCLK1 (36MHz) */
+       RCC->CFGR &= CFGR_PPRE1_RESET_MASK;
+       RCC->CFGR |= RCC_HCLK_DIV2;
+       /* Configure system clock dividers: HCLK */
+       RCC->CFGR &= CFGR_HPRE_RESET_MASK;
+       RCC->CFGR |= RCC_SYSCLK_DIV1;
+
        /* Set 1 wait state for the flash memory */
-       *(reg32_t *)0x40022000 = 0x12;
+       *(reg32_t *)FLASH_BASE = 0x12;
 
        /* Clock the system from the PLL */
        rcc_set_clock_source(RCC_SYSCLK_PLLCLK);