STM32: USB: device, interface and endpoint status is always uint16_t

[bertos.git] / bertos / cpu / cortex-m3 / drv / clock_stm32.c

diff --git a/bertos/cpu/cortex-m3/drv/clock_stm32.c b/bertos/cpu/cortex-m3/drv/clock_stm32.c
index 4b8cd89897de9982210badca6b9ccf3d5eefacc3..c1db8b6b1d18621fbbc688059930f2dcc190be04 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/clock_stm32.c
+++ b/bertos/cpu/cortex-m3/drv/clock_stm32.c
@@ -35,10 +35,12 @@
  * \author Andrea Righi <arighi@develer.com>
  */
 
+#include "clock_stm32.h"
+
 #include <cfg/compiler.h>
 #include <cfg/debug.h>
+
 #include <io/stm32.h>
-#include "clock_stm32.h"
 
 struct RCC *RCC;
 
@@ -66,7 +68,7 @@ INLINE int rcc_get_flag_status(uint32_t flag)
 
 INLINE uint16_t pll_clock(void)
 {
-       int div, mul;
+       unsigned int div, mul;
 
        /* Hopefully this is evaluate at compile time... */
        for (div = 2; div; div--)
@@ -136,7 +138,7 @@ void clock_init(void)
        RCC->CFGR |= RCC_HCLK_DIV1 << 3;
        /* Configure system clock dividers: PCLK1 (36MHz) */
        RCC->CFGR &= CFGR_PPRE1_RESET_MASK;
-       RCC->CFGR |= RCC_HCLK_DIV2 << 3;
+       RCC->CFGR |= RCC_HCLK_DIV2;
        /* Configure system clock dividers: HCLK */
        RCC->CFGR &= CFGR_HPRE_RESET_MASK;
        RCC->CFGR |= RCC_SYSCLK_DIV1;