reg32_t *ctrlb;
};
-#define DMAC_CHANNEL_CNT 5
+#define DMAC_CHANNEL_CNT 6
struct DmacCh dmac_ch[] =
{
{
},
};
-
/* We use event to signal the end of conversion */
-static Event data_ready;
static Dmac dmac[DMAC_CHANNEL_CNT];
static uint8_t dmac_ch_enabled;
-void dmac_configureDmacLLI(int ch, DmacDesc *lli, size_t transfer_size, uint32_t cfg, uint32_t ctrla, uint32_t ctrlb)
-{
- DMAC_CHDR = BV(ch);
-
- *dmac_ch[ch].cfg = cfg | DMAC_CFG_FIFOCFG_ALAP_CFG | (0x1 << DMAC_CFG_AHB_PROT_SHIFT);
- lli->ctrla = ctrla | (transfer_size & DMAC_CTRLA_BTSIZE_MASK);
- lli->ctrlb = ctrlb;// & ~BV(DMAC_CTRLB_IEN);
- *dmac_ch[ch].desc = (uint32_t)lli;
-}
-
-
-void dmac_configureDmaCfgLLI(int ch, DmacDesc *lli, uint32_t cfg)
+void dmac_setLLITransfer(int ch, DmacDesc *lli, uint32_t cfg)
{
DMAC_CHDR = BV(ch);
+ reg32_t reg = DMAC_EBCISR;
+ (void)reg;
*dmac_ch[ch].cfg = cfg | DMAC_CFG_FIFOCFG_ALAP_CFG | (0x1 << DMAC_CFG_AHB_PROT_SHIFT);
*dmac_ch[ch].desc = (uint32_t)lli;
{
DMAC_CHDR = BV(ch);
- *dmac_ch[ch].cfg = cfg | DMAC_CFG_FIFOCFG_ALAP_CFG | (0x1 << DMAC_CFG_AHB_PROT_SHIFT) | BV(DMAC_CFG_SOD);
+ *dmac_ch[ch].cfg = cfg | DMAC_CFG_FIFOCFG_ALAP_CFG | (0x1 << DMAC_CFG_AHB_PROT_SHIFT);
*dmac_ch[ch].ctrla = ctrla | (transfer_size & DMAC_CTRLA_BTSIZE_MASK);
*dmac_ch[ch].ctrlb = ctrlb & ~BV(DMAC_CTRLB_IEN);
}
return -1;
}
DMAC_CHER = BV(ch);
+ dmac_ch_enabled |= BV(ch);
return 0;
}
-int dmac_stop(int ch)
-{
- DMAC_CHDR = BV(ch);
- return 0;
-}
-
-bool dmac_isLLIDone(int ch)
-{
- return (DMAC_EBCIMR |= (BV(ch) << DMAC_EBCISR_CBTC0));
-}
-
-bool dmac_waitLLIDone(int ch)
-{
- while(!(DMAC_EBCIMR |= (BV(ch) << DMAC_EBCISR_CBTC0)))
- cpu_relax();
-
- DMAC_CHDR = BV(ch);
- return true;
-}
-
-bool dmac_isDone(int ch)
+void dmac_stop(int ch)
{
- //event_wait(&data_ready);
- return (*dmac_ch[ch].ctrla & BV(31));//(DMAC_CHSR |= (BV(dmac->ch) << DMAC_CHSR_EMPT0));
-}
-
-bool dmac_waitDone(int ch)
-{
- event_wait(&data_ready);
DMAC_CHDR = BV(ch);
- return true;
+ dmac_ch_enabled &= ~BV(ch);
}
int dmac_error(int ch)