Some cosmetic fixes.

[bertos.git] / bertos / cpu / cortex-m3 / drv / eth_sam3.c

diff --git a/bertos/cpu/cortex-m3/drv/eth_sam3.c b/bertos/cpu/cortex-m3/drv/eth_sam3.c
index f83dba7227d71d4ffe551045eb23d82fd2ab6462..187041f21bb1664541b18a24f8c0c696a18a09ae 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/eth_sam3.c
+++ b/bertos/cpu/cortex-m3/drv/eth_sam3.c
@@ -234,22 +234,10 @@ static int emac_reset(void)
        pmc_periphEnable(PIOD_ID);
        pmc_periphEnable(EMAC_ID);
 
-       // Disable TESTMODE and RMII
-       PIOC_PUDR = BV(PHY_RXDV_TESTMODE_BIT);
-
-       // Disable PHY power down.
-       PIOD_PER  = BV(PHY_PWRDN_BIT);
-       PIOD_OER  = BV(PHY_PWRDN_BIT);
-       PIOD_CODR = BV(PHY_PWRDN_BIT);
+       // Disable TESTMODE
+       PIOB_PUDR = BV(PHY_RXDV_TESTMODE_BIT);
 #endif
 
-       // Toggle external hardware reset pin.
-       RSTC_MR = RSTC_KEY | (1 << RSTC_ERSTL_SHIFT) | BV(RSTC_URSTEN);
-       RSTC_CR = RSTC_KEY | BV(RSTC_EXTRST);
-
-       while ((RSTC_SR & BV(RSTC_NRSTL)) == 0)
-               cpu_relax();
-
        // Configure MII ports.
 #if CPU_ARM_AT91
        PIOB_ASR = PHY_MII_PINS;
@@ -262,9 +250,6 @@ static int emac_reset(void)
        PIO_PERIPH_SEL(PIOB_BASE, PHY_MII_PINS_PORTB, PIO_PERIPH_A);
        PIOB_PDR = PHY_MII_PINS_PORTB;
 
-       PIO_PERIPH_SEL(PIOC_BASE, PHY_MII_PINS_PORTC, PIO_PERIPH_A);
-       PIOC_PDR = PHY_MII_PINS_PORTC;
-
        // Enable receive, transmit clocks and RMII mode.
        EMAC_USRIO = BV(EMAC_CLKEN) | BV(EMAC_RMII);
 #endif