Remove duplicate define. Put all phy chip specific defines in its

[bertos.git] / bertos / cpu / cortex-m3 / drv / eth_sam3.c

diff --git a/bertos/cpu/cortex-m3/drv/eth_sam3.c b/bertos/cpu/cortex-m3/drv/eth_sam3.c
index 0247f6181e26fe1c2065e16a3d81dd5051014a99..58859e59e6646f967a9fab7634b1bf1c4020dca3 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/eth_sam3.c
+++ b/bertos/cpu/cortex-m3/drv/eth_sam3.c
@@ -37,6 +37,7 @@
   * \author Stefano Fedrigo <aleph@develer.com>
   */
 
+#include "eth_sam3.h"
 #include "cfg/cfg_eth.h"
 
 #define LOG_LEVEL  ETH_LOG_LEVEL
@@ -49,36 +50,23 @@
 #include <cfg/macros.h>
 #include <cfg/compiler.h>
 
-// TODO: unify includes
-//#include <io/at91sam7.h>
-//#include <io/arm.h>
-//#include <io/include.h>
-#include <io/sam3.h>
+#include <io/cm3.h>
+
 #include <drv/irq_cm3.h>
+#include <drv/timer.h>
+#include <drv/eth.h>
 
 #include <cpu/power.h>
 #include <cpu/types.h>
 #include <cpu/irq.h>
 
-#include <drv/timer.h>
-#include <drv/eth.h>
-
 #include <mware/event.h>
 
 #include <string.h>
 
-#include "eth_sam3.h"
-
 #define EMAC_RX_INTS   (BV(EMAC_RCOMP) | BV(EMAC_ROVR) | BV(EMAC_RXUBR))
 #define EMAC_TX_INTS   (BV(EMAC_TCOMP) | BV(EMAC_TXUBR) | BV(EMAC_RLEX))
 
-/*
- * MAC address configuration (please change this in your project!).
- *
- * TODO: make this paramater user-configurable from the Wizard.
- */
-const uint8_t mac_addr[] = { 0x00, 0x45, 0x56, 0x78, 0x9a, 0xbc };
-
 /* Silent Doxygen bug... */
 #ifndef __doxygen__
 /*
@@ -241,22 +229,10 @@ static int emac_reset(void)
        pmc_periphEnable(PIOD_ID);
        pmc_periphEnable(EMAC_ID);
 
-       // Disable TESTMODE and RMII
-       PIOC_PUDR = BV(PHY_RXDV_TESTMODE_BIT);
-
-       // Disable PHY power down.
-       PIOD_PER  = BV(PHY_PWRDN_BIT);
-       PIOD_OER  = BV(PHY_PWRDN_BIT);
-       PIOD_CODR = BV(PHY_PWRDN_BIT);
+       // Disable TESTMODE
+       PIOB_PUDR = BV(PHY_RXDV_TESTMODE_BIT);
 #endif
 
-       // Toggle external hardware reset pin.
-       RSTC_MR = RSTC_KEY | (1 << RSTC_ERSTL_SHIFT) | BV(RSTC_URSTEN);
-       RSTC_CR = RSTC_KEY | BV(RSTC_EXTRST);
-
-       while ((RSTC_SR & BV(RSTC_NRSTL)) == 0)
-               cpu_relax();
-
        // Configure MII ports.
 #if CPU_ARM_AT91
        PIOB_ASR = PHY_MII_PINS;
@@ -269,9 +245,6 @@ static int emac_reset(void)
        PIO_PERIPH_SEL(PIOB_BASE, PHY_MII_PINS_PORTB, PIO_PERIPH_A);
        PIOB_PDR = PHY_MII_PINS_PORTB;
 
-       PIO_PERIPH_SEL(PIOC_BASE, PHY_MII_PINS_PORTC, PIO_PERIPH_A);
-       PIOC_PDR = PHY_MII_PINS_PORTC;
-
        // Enable receive, transmit clocks and RMII mode.
        EMAC_USRIO = BV(EMAC_CLKEN) | BV(EMAC_RMII);
 #endif