sam3 eth: handle phy addr in phy maintenance functions; increase management

[bertos.git] / bertos / cpu / cortex-m3 / drv / eth_sam3.h

diff --git a/bertos/cpu/cortex-m3/drv/eth_sam3.h b/bertos/cpu/cortex-m3/drv/eth_sam3.h
index f733df9a4afd38244b2a8f3aa61dd0c9b943e2eb..04d4aab68c2fddf345573867db341abd7bc30967 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/eth_sam3.h
+++ b/bertos/cpu/cortex-m3/drv/eth_sam3.h
@@ -42,7 +42,7 @@
 
 // Settings and definition for DAVICOM 9161A
 // \{
-#define NIC_PHY_ADDR            31
+#define NIC_PHY_ADDR            0
 
 //Registry definition
 #define NIC_PHY_BMCR            0x00    //  Basic mode control register.