Add missing define.

[bertos.git] / bertos / cpu / cortex-m3 / drv / hsmci_sam3.c

diff --git a/bertos/cpu/cortex-m3/drv/hsmci_sam3.c b/bertos/cpu/cortex-m3/drv/hsmci_sam3.c
index 13b2f1367940f033cde1202e68edc28a86b41c22..3cd4a4eaac2163a425ff53f54a69161dbc5c6734 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/hsmci_sam3.c
+++ b/bertos/cpu/cortex-m3/drv/hsmci_sam3.c
@@ -61,13 +61,19 @@
 
 
 #define HSMCI_RESP_ERROR_MASK   (BV(HSMCI_SR_RINDE) | BV(HSMCI_SR_RDIRE) \
-       | BV(HSMCI_SR_RCRCE)| BV(HSMCI_SR_RENDE)| BV(HSMCI_SR_RTOE))
-
+         | BV(HSMCI_SR_RENDE)| BV(HSMCI_SR_RTOE))
 
+#define HSMCI_READY_MASK     (BV(HSMCI_SR_CMDRDY) | BV(HSMCI_SR_NOTBUSY))
 #define HSMCI_WAIT()\
        do { \
                cpu_relax(); \
-       } while (!(HSMCI_SR & (BV(HSMCI_SR_CMDRDY) | BV(HSMCI_SR_NOTBUSY) | BV(HSMCI_SR_XFRDONE))))
+       } while (!(HSMCI_SR & BV(HSMCI_SR_CMDRDY)))
+
+
+#define HSMCI_WAIT_DATA_RDY()\
+       do { \
+               cpu_relax(); \
+       } while (!(HSMCI_SR & BV(HSMCI_SR_RXRDY)))
 
 #define HSMCI_ERROR()   (HSMCI_SR & HSMCI_ERROR_MASK)
 
@@ -88,7 +94,11 @@ do { \
 
 static DECLARE_ISR(hsmci_irq)
 {
-       kprintf("irq stato %lx\n", HSMCI_SR);
+       if (HSMCI_SR & BV(HSMCI_IER_RTOE))
+       {
+               HSMCI_ARGR = 0;
+               HSMCI_CMDR = 0 | HSMCI_CMDR_RSPTYP_NORESP | BV(HSMCI_CMDR_OPDCMD);
+       }
 }
 
 void hsmci_readResp(void *resp, size_t len)
@@ -96,8 +106,7 @@ void hsmci_readResp(void *resp, size_t len)
        ASSERT(resp);
        uint32_t *r = (uint32_t *)resp;
 
-       kprintf("size %d %d\n",(len / sizeof(HSMCI_RSPR)),  sizeof(HSMCI_RSPR));
-       for (size_t i = 0; i < (len / sizeof(HSMCI_RSPR)); i++)
+       for (size_t i = 0; i < len ; i++)
                r[i] = HSMCI_RSPR;
 }
 
@@ -107,22 +116,54 @@ bool hsmci_sendCmd(uint8_t index, uint32_t argument, uint32_t reply_type)
        HSMCI_WAIT();
 
        HSMCI_ARGR = argument;
-       HSMCI_CMDR = index | reply_type | BV(HSMCI_CMDR_OPDCMD);
+       HSMCI_CMDR = index | reply_type | BV(HSMCI_CMDR_MAXLAT) | BV(HSMCI_CMDR_OPDCMD);
 
-       uint32_t status;
-       do {
-               status = HSMCI_SR;
+       uint32_t status = HSMCI_SR;
+       while (!(status & BV(HSMCI_SR_CMDRDY)))
+       {
                if (status & HSMCI_RESP_ERROR_MASK)
                        return status;
 
                cpu_relax();
-       } while (!(status & (BV(HSMCI_SR_CMDRDY) | BV(HSMCI_SR_NOTBUSY) | BV(HSMCI_SR_XFRDONE))));
 
-       timer_delay(1);
+               status = HSMCI_SR;
+       }
+
        STROBE_OFF();
        return 0;
 }
 
+void hsmci_setBlkSize(size_t blk_size)
+{
+       HSMCI_DMA = BV(HSMCI_DMA_DMAEN);
+       HSMCI_BLKR = (blk_size << HSMCI_BLKR_BLKLEN_SHIFT);
+}
+
+bool hsmci_read(uint32_t *buf, size_t word_num)
+{
+       ASSERT(buf);
+       ASSERT(!(DMAC_CHSR & BV(DMAC_CHSR_ENA0)));
+
+       kprintf("DMAC status %08lx channel st %08lx\n", DMAC_EBCISR, DMAC_CHSR);
+
+       DMAC_SADDR0 = 0x40000200U;
+       DMAC_DADDR0 = (uint32_t)buf;
+       DMAC_DSCR0 = 0;
+
+       DMAC_CTRLA0 = word_num | DMAC_CTRLA_SRC_WIDTH_WORD | DMAC_CTRLA_DST_WIDTH_WORD;
+       DMAC_CTRLB0 = (BV(DMAC_CTRLB_SRC_DSCR) | DMAC_CTRLB_FC_PER2MEM_DMA_FC |
+                                       DMAC_CTRLB_SRC_INCR_FIXED | DMAC_CTRLB_DST_INCR_INCREMENTING | BV(DMAC_CTRLB_IEN));
+
+       ASSERT(!(DMAC_CHSR & BV(DMAC_CHSR_ENA0)));
+       DMAC_CHER = BV(DMAC_CHER_ENA0);
+
+       while (!(HSMCI_SR & BV(HSMCI_SR_XFRDONE)))
+               cpu_relax();
+
+       DMAC_CHDR = BV(DMAC_CHDR_DIS0);
+       return 0;
+}
+
 void hsmci_init(Hsmci *hsmci)
 {
        (void)hsmci;
@@ -137,11 +178,23 @@ void hsmci_init(Hsmci *hsmci)
 
        HSMCI_DTOR = 0xFF | HSMCI_DTOR_DTOMUL_1048576;
        HSMCI_CSTOR = 0xFF | HSMCI_CSTOR_CSTOMUL_1048576;
-       HSMCI_MR = HSMCI_CLK_DIV | ((0x7u << HSMCI_MR_PWSDIV_SHIFT) & HSMCI_MR_PWSDIV_MASK);
+       HSMCI_MR = HSMCI_CLK_DIV | ((0x7u << HSMCI_MR_PWSDIV_SHIFT) & HSMCI_MR_PWSDIV_MASK) | BV(HSMCI_MR_RDPROOF);
        HSMCI_SDCR = 0;
        HSMCI_CFG = BV(HSMCI_CFG_FIFOMODE) | BV(HSMCI_CFG_FERRCTRL);
 
        sysirq_setHandler(INT_HSMCI, hsmci_irq);
        HSMCI_CR = BV(HSMCI_CR_MCIEN);
+       HSMCI_DMA &= ~BV(HSMCI_DMA_DMAEN);
+
+       //init DMAC
+       DMAC_EBCIDR = 0x3FFFFF;
+       DMAC_CHDR = BV(DMAC_CHDR_DIS0);
+
+       DMAC_CFG0 = 0;
+       DMAC_CFG0 = BV(DMAC_CFG_SRC_H2SEL) | DMAC_CFG_FIFOCFG_ALAP_CFG | BV(DMAC_CFG_SOD);
+
+       pmc_periphEnable(DMAC_ID);
+       DMAC_EN = BV(DMAC_EN_ENABLE);
 
+       //HSMCI_IER = BV(HSMCI_IER_RTOE);
 }