#include "hsmci_sam3.h"
+#include "hw/hw_sd.h"
#include <drv/timer.h>
-#include <cpu/irq.h>
#include <drv/irq_cm3.h>
+#include <cpu/irq.h>
+
#include <io/cm3.h>
/** DMA Transfer Descriptor as well as Linked List Item */
uint32_t dsc_addr; /**< Next descriptor address */
} DmacDesc;
-
-
-
#define HSMCI_CLK_DIV(RATE) ((CPU_FREQ / (RATE << 1)) - 1)
-#define HSMCI_ERROR_MASK (BV(HSMCI_SR_RINDE) | \
- BV(HSMCI_SR_RDIRE) | \
- BV(HSMCI_SR_RCRCE) | \
- BV(HSMCI_SR_RENDE) | \
- BV(HSMCI_SR_RTOE) | \
- BV(HSMCI_SR_DCRCE) | \
- BV(HSMCI_SR_DTOE) | \
- BV(HSMCI_SR_CSTOE) | \
- BV(HSMCI_SR_BLKOVRE) | \
- BV(HSMCI_SR_ACKRCVE))
-
#define HSMCI_RESP_ERROR_MASK (BV(HSMCI_SR_RINDE) | BV(HSMCI_SR_RDIRE) \
| BV(HSMCI_SR_RENDE)| BV(HSMCI_SR_RTOE))
cpu_relax(); \
} while (!(HSMCI_SR & BV(HSMCI_SR_RXRDY)))
-#define HSMCI_ERROR() (HSMCI_SR & HSMCI_ERROR_MASK)
-
-#define HSMCI_HW_INIT() \
-do { \
- PIOA_PDR = BV(19) | BV(20) | BV(21) | BV(22) | BV(23) | BV(24); \
- PIO_PERIPH_SEL(PIOA_BASE, BV(19) | BV(20) | BV(21) | BV(22) | BV(23) | BV(24), PIO_PERIPH_A); \
-} while (0)
-
-
-#define STROBE_ON() PIOB_SODR = BV(13)
-#define STROBE_OFF() PIOB_CODR = BV(13)
-#define STROBE_INIT() \
- do { \
- PIOB_OER = BV(13); \
- PIOB_PER = BV(13); \
- } while(0)
-
static DECLARE_ISR(hsmci_irq)
{
uint32_t status = HSMCI_SR;
}
}
-
static DECLARE_ISR(dmac_irq)
{
uint32_t stat = DMAC_EBCISR;
bool hsmci_sendCmd(uint8_t index, uint32_t argument, uint32_t reply_type)
{
- STROBE_ON();
HSMCI_WAIT();
HSMCI_ARGR = argument;
status = HSMCI_SR;
}
- STROBE_OFF();
return 0;
}
HSMCI_BLKR = blk_size << HSMCI_BLKR_BLKLEN_SHIFT;
}
-void hsmci_prgTxDMA(uint32_t *buf, size_t word_num, size_t blk_size)
+void hsmci_prgTxDMA(const uint32_t *buf, size_t word_num, size_t blk_size)
{
hsmci_setBlockSize(blk_size);
{
(void)hsmci;
- HSMCI_HW_INIT();
- STROBE_INIT();
+ SD_PIN_INIT();
pmc_periphEnable(HSMCI_ID);
HSMCI_CR = BV(HSMCI_CR_SWRST);
DMAC_EBCIDR = 0x3FFFFF;
DMAC_CHDR = 0x1F;
-
pmc_periphEnable(DMAC_ID);
DMAC_EN = BV(DMAC_EN_ENABLE);
sysirq_setHandler(INT_DMAC, dmac_irq);