Move some define in sam3x sd implementaion. Define sd speeds macro to clarify the...

[bertos.git] / bertos / cpu / cortex-m3 / drv / hsmci_sam3.c

diff --git a/bertos/cpu/cortex-m3/drv/hsmci_sam3.c b/bertos/cpu/cortex-m3/drv/hsmci_sam3.c
index b32d688be173e9adac02914c16f7449f0d6cdf3a..d09723fc146601be8a16b8a01ab61a949299e0a8 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/hsmci_sam3.c
+++ b/bertos/cpu/cortex-m3/drv/hsmci_sam3.c
@@ -36,11 +36,13 @@
 
 
 #include "hsmci_sam3.h"
+#include "hw/hw_sd.h"
 
 #include <drv/timer.h>
-#include <cpu/irq.h>
 #include <drv/irq_cm3.h>
 
+#include <cpu/irq.h>
+
 #include <io/cm3.h>
 
 /** DMA Transfer Descriptor as well as Linked List Item */
@@ -53,22 +55,8 @@ typedef struct DmacDesc
     uint32_t dsc_addr;     /**< Next descriptor address */
 } DmacDesc;
 
-
-
-
 #define HSMCI_CLK_DIV(RATE)     ((CPU_FREQ / (RATE << 1)) - 1)
 
-#define HSMCI_ERROR_MASK   (BV(HSMCI_SR_RINDE)    | \
-                                                       BV(HSMCI_SR_RDIRE)    | \
-                                                       BV(HSMCI_SR_RCRCE)    | \
-                                                       BV(HSMCI_SR_RENDE)    | \
-                                                       BV(HSMCI_SR_RTOE)     | \
-                                                       BV(HSMCI_SR_DCRCE)    | \
-                                                       BV(HSMCI_SR_DTOE)     | \
-                                                       BV(HSMCI_SR_CSTOE)    | \
-                                                       BV(HSMCI_SR_BLKOVRE)  | \
-                                                       BV(HSMCI_SR_ACKRCVE))
-
 
 #define HSMCI_RESP_ERROR_MASK   (BV(HSMCI_SR_RINDE) | BV(HSMCI_SR_RDIRE) \
          | BV(HSMCI_SR_RENDE)| BV(HSMCI_SR_RTOE))
@@ -87,33 +75,14 @@ typedef struct DmacDesc
                cpu_relax(); \
        } while (!(HSMCI_SR & BV(HSMCI_SR_RXRDY)))
 
-#define HSMCI_ERROR()   (HSMCI_SR & HSMCI_ERROR_MASK)
-
-#define HSMCI_HW_INIT()  \
-do { \
-       PIOA_PDR = BV(19) | BV(20) | BV(21) | BV(22) | BV(23) | BV(24); \
-       PIO_PERIPH_SEL(PIOA_BASE, BV(19) | BV(20) | BV(21) | BV(22) | BV(23) | BV(24), PIO_PERIPH_A); \
-} while (0)
-
-
-#define STROBE_ON()   PIOB_SODR = BV(13)
-#define STROBE_OFF()  PIOB_CODR = BV(13)
-#define STROBE_INIT() \
-       do { \
-               PIOB_OER = BV(13); \
-               PIOB_PER = BV(13); \
-       } while(0)
-
 static DECLARE_ISR(hsmci_irq)
 {
        uint32_t status = HSMCI_SR;
        if (status & BV(HSMCI_IER_DMADONE))
        {
-               kputs("\n\nfatto\n\n");
        }
 }
 
-
 static DECLARE_ISR(dmac_irq)
 {
        uint32_t stat = DMAC_EBCISR;
@@ -134,11 +103,10 @@ void hsmci_readResp(uint32_t *resp, size_t len)
 
 bool hsmci_sendCmd(uint8_t index, uint32_t argument, uint32_t reply_type)
 {
-       STROBE_ON();
        HSMCI_WAIT();
 
        HSMCI_ARGR = argument;
-       HSMCI_CMDR = index | reply_type | BV(HSMCI_CMDR_MAXLAT);// | BV(HSMCI_CMDR_OPDCMD);
+       HSMCI_CMDR = index | reply_type | BV(HSMCI_CMDR_MAXLAT);
 
        uint32_t status = HSMCI_SR;
        while (!(status & BV(HSMCI_SR_CMDRDY)))
@@ -151,18 +119,16 @@ bool hsmci_sendCmd(uint8_t index, uint32_t argument, uint32_t reply_type)
                status = HSMCI_SR;
        }
 
-       STROBE_OFF();
        return 0;
 }
 
 INLINE void hsmci_setBlockSize(size_t blk_size)
 {
-       HSMCI_IER = BV(HSMCI_IER_DMADONE);
        HSMCI_DMA |= BV(HSMCI_DMA_DMAEN);
        HSMCI_BLKR = blk_size << HSMCI_BLKR_BLKLEN_SHIFT;
 }
 
-void hsmci_prgTxDMA(uint32_t *buf, size_t word_num, size_t blk_size)
+void hsmci_prgTxDMA(const uint32_t *buf, size_t word_num, size_t blk_size)
 {
 
        hsmci_setBlockSize(blk_size);
@@ -173,18 +139,12 @@ void hsmci_prgTxDMA(uint32_t *buf, size_t word_num, size_t blk_size)
        DMAC_DADDR0 = (uint32_t)&HSMCI_TDR;
        DMAC_DSCR0 = 0;
 
+       DMAC_CFG0 = BV(DMAC_CFG_DST_H2SEL) | DMAC_CFG_FIFOCFG_ALAP_CFG | (0x1 << DMAC_CFG_AHB_PROT_SHIFT);
        DMAC_CTRLA0 = (word_num & DMAC_CTRLA_BTSIZE_MASK) |
                DMAC_CTRLA_SRC_WIDTH_WORD | DMAC_CTRLA_DST_WIDTH_WORD;
        DMAC_CTRLB0 = (BV(DMAC_CTRLB_SRC_DSCR) | BV(DMAC_CTRLB_DST_DSCR) | DMAC_CTRLB_FC_MEM2PER_DMA_FC |
                                        DMAC_CTRLB_DST_INCR_FIXED | DMAC_CTRLB_SRC_INCR_INCREMENTING | BV(DMAC_CTRLB_IEN));
 
-       kprintf("SDDR %08lx\n", DMAC_SADDR0);
-       kprintf("DDDR %08lx\n", DMAC_DADDR0);
-       kprintf("CTRA %08lx\n", DMAC_CTRLA0);
-       kprintf("CTRB %08lx\n", DMAC_CTRLB0);
-       kprintf("EBCI %08lx\n", DMAC_EBCISR);
-       kprintf("CHSR %08lx\n", DMAC_CHSR);
-
        ASSERT(!(DMAC_CHSR & BV(DMAC_CHSR_ENA0)));
        DMAC_CHER = BV(DMAC_CHER_ENA0);
 
@@ -200,18 +160,12 @@ void hsmci_prgRxDMA(uint32_t *buf, size_t word_num, size_t blk_size)
        DMAC_DADDR0 = (uint32_t)buf;
        DMAC_DSCR0 = 0;
 
+       DMAC_CFG0 = BV(DMAC_CFG_SRC_H2SEL) | DMAC_CFG_FIFOCFG_ALAP_CFG | (0x1 << DMAC_CFG_AHB_PROT_SHIFT);
        DMAC_CTRLA0 = (word_num & DMAC_CTRLA_BTSIZE_MASK) |
                DMAC_CTRLA_SRC_WIDTH_WORD | DMAC_CTRLA_DST_WIDTH_WORD;
        DMAC_CTRLB0 = (BV(DMAC_CTRLB_SRC_DSCR) | BV(DMAC_CTRLB_DST_DSCR) | DMAC_CTRLB_FC_PER2MEM_DMA_FC |
                                        DMAC_CTRLB_DST_INCR_INCREMENTING | DMAC_CTRLB_SRC_INCR_FIXED | BV(DMAC_CTRLB_IEN));
 
-       kprintf("SDDR %08lx\n", DMAC_SADDR0);
-       kprintf("DDDR %08lx\n", DMAC_DADDR0);
-       kprintf("CTRA %08lx\n", DMAC_CTRLA0);
-       kprintf("CTRB %08lx\n", DMAC_CTRLB0);
-       kprintf("EBCI %08lx\n", DMAC_EBCISR);
-       kprintf("CHSR %08lx\n", DMAC_CHSR);
-
        ASSERT(!(DMAC_CHSR & BV(DMAC_CHSR_ENA0)));
        DMAC_CHER = BV(DMAC_CHER_ENA0);
 }
@@ -225,7 +179,7 @@ void hsmci_waitTransfer(void)
 
 void hsmci_setSpeed(uint32_t data_rate, int flag)
 {
-       if (flag)
+       if (flag & HSMCI_HS_MODE)
                HSMCI_CFG |= BV(HSMCI_CFG_HSMODE);
        else
                HSMCI_CFG &= ~BV(HSMCI_CFG_HSMODE);
@@ -239,8 +193,7 @@ void hsmci_init(Hsmci *hsmci)
 {
        (void)hsmci;
 
-       HSMCI_HW_INIT();
-       STROBE_INIT();
+       SD_PIN_INIT();
 
        pmc_periphEnable(HSMCI_ID);
        HSMCI_CR = BV(HSMCI_CR_SWRST);
@@ -256,16 +209,13 @@ void hsmci_init(Hsmci *hsmci)
        HSMCI_CR = BV(HSMCI_CR_MCIEN);
        HSMCI_DMA = 0;
 
-
        //init DMAC
        DMAC_EBCIDR = 0x3FFFFF;
        DMAC_CHDR = 0x1F;
-       DMAC_CFG0 = BV(DMAC_CFG_SRC_H2SEL) | DMAC_CFG_FIFOCFG_ALAP_CFG | (0x1 << DMAC_CFG_AHB_PROT_SHIFT);
 
        pmc_periphEnable(DMAC_ID);
        DMAC_EN = BV(DMAC_EN_ENABLE);
        sysirq_setHandler(INT_DMAC, dmac_irq);
 
        DMAC_EBCIER = BV(DMAC_EBCIER_BTC0) | BV(DMAC_EBCIER_ERR0);
-
 }