#include "hsmci_sam3.h"
+#include "hw/hw_sd.h"
#include <drv/timer.h>
-#include <cpu/irq.h>
#include <drv/irq_cm3.h>
+#include <drv/dmac_sam3.h>
-#include <io/cm3.h>
-
-/** DMA Transfer Descriptor as well as Linked List Item */
-typedef struct DmacDesc
-{
- uint32_t src_addr; /**< Source buffer address */
- uint32_t dst_addr; /**< Destination buffer address */
- uint32_t ctrl_a; /**< Control A register settings */
- uint32_t ctrl_b; /**< Control B register settings */
- uint32_t dsc_addr; /**< Next descriptor address */
-} DmacDesc;
+#include <mware/event.h>
+#include <cpu/irq.h>
+#include <io/cm3.h>
#define HSMCI_CLK_DIV(RATE) ((CPU_FREQ / (RATE << 1)) - 1)
-#define HSMCI_ERROR_MASK (BV(HSMCI_SR_RINDE) | \
- BV(HSMCI_SR_RDIRE) | \
- BV(HSMCI_SR_RCRCE) | \
- BV(HSMCI_SR_RENDE) | \
- BV(HSMCI_SR_RTOE) | \
- BV(HSMCI_SR_DCRCE) | \
- BV(HSMCI_SR_DTOE) | \
- BV(HSMCI_SR_CSTOE) | \
- BV(HSMCI_SR_BLKOVRE) | \
- BV(HSMCI_SR_ACKRCVE))
-
#define HSMCI_RESP_ERROR_MASK (BV(HSMCI_SR_RINDE) | BV(HSMCI_SR_RDIRE) \
| BV(HSMCI_SR_RENDE)| BV(HSMCI_SR_RTOE))
cpu_relax(); \
} while (!(HSMCI_SR & BV(HSMCI_SR_RXRDY)))
-#define HSMCI_ERROR() (HSMCI_SR & HSMCI_ERROR_MASK)
-
-#define HSMCI_HW_INIT() \
-do { \
- PIOA_PDR = BV(19) | BV(20) | BV(21) | BV(22) | BV(23) | BV(24); \
- PIO_PERIPH_SEL(PIOA_BASE, BV(19) | BV(20) | BV(21) | BV(22) | BV(23) | BV(24), PIO_PERIPH_A); \
-} while (0)
+#define HSMCI_DMAC_CH 3
-#define STROBE_ON() PIOB_SODR = BV(13)
-#define STROBE_OFF() PIOB_CODR = BV(13)
-#define STROBE_INIT() \
- do { \
- PIOB_OER = BV(13); \
- PIOB_PER = BV(13); \
- } while(0)
-
-static DECLARE_ISR(hsmci_irq)
-{
- uint32_t status = HSMCI_SR;
- if (status & BV(HSMCI_IER_DMADONE))
- {
- }
-}
-
-
-static DECLARE_ISR(dmac_irq)
-{
- uint32_t stat = DMAC_EBCISR;
-
- if (stat & BV(DMAC_EBCISR_ERR3))
- {
- kprintf("err %08lx\n", stat);
- }
-}
void hsmci_readResp(uint32_t *resp, size_t len)
{
bool hsmci_sendCmd(uint8_t index, uint32_t argument, uint32_t reply_type)
{
- STROBE_ON();
HSMCI_WAIT();
HSMCI_ARGR = argument;
status = HSMCI_SR;
}
- STROBE_OFF();
return 0;
}
-INLINE void hsmci_setBlockSize(size_t blk_size)
-{
- HSMCI_DMA |= BV(HSMCI_DMA_DMAEN);
- HSMCI_BLKR = blk_size << HSMCI_BLKR_BLKLEN_SHIFT;
-}
-
-void hsmci_prgTxDMA(const uint32_t *buf, size_t word_num, size_t blk_size)
-{
+#define HSMCI_WRITE_DMAC_CFG (BV(DMAC_CFG_DST_H2SEL) | \
+ BV(DMAC_CFG_SOD) | \
+ ((0 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | \
+ (0 & DMAC_CFG_SRC_PER_MASK))
- hsmci_setBlockSize(blk_size);
+#define HSMCI_WRITE_DMAC_CTRLB (BV(DMAC_CTRLB_SRC_DSCR) | BV(DMAC_CTRLB_DST_DSCR) | \
+ DMAC_CTRLB_FC_MEM2PER_DMA_FC | \
+ DMAC_CTRLB_DST_INCR_FIXED | DMAC_CTRLB_SRC_INCR_INCREMENTING)
- DMAC_CHDR = BV(DMAC_CHDR_DIS0);
+#define HSMCI_WRITE_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_WORD | \
+ DMAC_CTRLA_DST_WIDTH_WORD)
- DMAC_SADDR0 = (uint32_t)buf;
- DMAC_DADDR0 = (uint32_t)&HSMCI_TDR;
- DMAC_DSCR0 = 0;
+#define HSMCI_READ_DMAC_CFG (BV(DMAC_CFG_SRC_H2SEL) | \
+ BV(DMAC_CFG_SOD) | \
+ ((0 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | \
+ (0 & DMAC_CFG_SRC_PER_MASK))
- DMAC_CFG0 = BV(DMAC_CFG_DST_H2SEL) | DMAC_CFG_FIFOCFG_ALAP_CFG | (0x1 << DMAC_CFG_AHB_PROT_SHIFT);
- DMAC_CTRLA0 = (word_num & DMAC_CTRLA_BTSIZE_MASK) |
- DMAC_CTRLA_SRC_WIDTH_WORD | DMAC_CTRLA_DST_WIDTH_WORD;
- DMAC_CTRLB0 = (BV(DMAC_CTRLB_SRC_DSCR) | BV(DMAC_CTRLB_DST_DSCR) | DMAC_CTRLB_FC_MEM2PER_DMA_FC |
- DMAC_CTRLB_DST_INCR_FIXED | DMAC_CTRLB_SRC_INCR_INCREMENTING | BV(DMAC_CTRLB_IEN));
+#define HSMCI_READ_DMAC_CTRLB (BV(DMAC_CTRLB_SRC_DSCR) | BV(DMAC_CTRLB_DST_DSCR) | \
+ DMAC_CTRLB_FC_PER2MEM_DMA_FC | \
+ DMAC_CTRLB_DST_INCR_INCREMENTING | DMAC_CTRLB_SRC_INCR_FIXED)
- ASSERT(!(DMAC_CHSR & BV(DMAC_CHSR_ENA0)));
- DMAC_CHER = BV(DMAC_CHER_ENA0);
+#define HSMCI_READ_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_WORD | \
+ DMAC_CTRLA_DST_WIDTH_WORD)
-}
-void hsmci_prgRxDMA(uint32_t *buf, size_t word_num, size_t blk_size)
+void hsmci_write(const uint32_t *buf, size_t word_num, size_t blk_size)
{
- hsmci_setBlockSize(blk_size);
-
- DMAC_CHDR = BV(DMAC_CHDR_DIS0);
+ HSMCI_DMA |= BV(HSMCI_DMA_DMAEN);
+ HSMCI_BLKR = (blk_size << HSMCI_BLKR_BLKLEN_SHIFT) & ~0x30000;
- DMAC_SADDR0 = (uint32_t)&HSMCI_RDR;
- DMAC_DADDR0 = (uint32_t)buf;
- DMAC_DSCR0 = 0;
+ dmac_setSources(HSMCI_DMAC_CH, (uint32_t)buf, (uint32_t)&HSMCI_TDR);
+ dmac_configureDmac(HSMCI_DMAC_CH, word_num, HSMCI_WRITE_DMAC_CFG, HSMCI_WRITE_DMAC_CTRLA, HSMCI_WRITE_DMAC_CTRLB);
+ dmac_start(HSMCI_DMAC_CH);
+}
- DMAC_CFG0 = BV(DMAC_CFG_SRC_H2SEL) | DMAC_CFG_FIFOCFG_ALAP_CFG | (0x1 << DMAC_CFG_AHB_PROT_SHIFT);
- DMAC_CTRLA0 = (word_num & DMAC_CTRLA_BTSIZE_MASK) |
- DMAC_CTRLA_SRC_WIDTH_WORD | DMAC_CTRLA_DST_WIDTH_WORD;
- DMAC_CTRLB0 = (BV(DMAC_CTRLB_SRC_DSCR) | BV(DMAC_CTRLB_DST_DSCR) | DMAC_CTRLB_FC_PER2MEM_DMA_FC |
- DMAC_CTRLB_DST_INCR_INCREMENTING | DMAC_CTRLB_SRC_INCR_FIXED | BV(DMAC_CTRLB_IEN));
+void hsmci_read(uint32_t *buf, size_t word_num, size_t blk_size)
+{
+ HSMCI_DMA |= BV(HSMCI_DMA_DMAEN);
+ HSMCI_BLKR = blk_size << HSMCI_BLKR_BLKLEN_SHIFT;
- ASSERT(!(DMAC_CHSR & BV(DMAC_CHSR_ENA0)));
- DMAC_CHER = BV(DMAC_CHER_ENA0);
+ dmac_setSources(HSMCI_DMAC_CH, (uint32_t)&HSMCI_RDR, (uint32_t)buf);
+ dmac_configureDmac(HSMCI_DMAC_CH, word_num, HSMCI_READ_DMAC_CFG, HSMCI_READ_DMAC_CTRLA, HSMCI_READ_DMAC_CTRLB);
+ dmac_start(HSMCI_DMAC_CH);
}
void hsmci_setSpeed(uint32_t data_rate, int flag)
{
- if (flag)
+ if (flag & HSMCI_HS_MODE)
HSMCI_CFG |= BV(HSMCI_CFG_HSMODE);
else
HSMCI_CFG &= ~BV(HSMCI_CFG_HSMODE);
- HSMCI_MR = HSMCI_CLK_DIV(data_rate) | ((0x7u << HSMCI_MR_PWSDIV_SHIFT) & HSMCI_MR_PWSDIV_MASK);
+ HSMCI_DTOR = 0xF8 | HSMCI_DTOR_DTOMUL_1;
+ HSMCI_CSTOR = 0xF8 | HSMCI_CSTOR_CSTOMUL_1;
+ HSMCI_MR = HSMCI_CLK_DIV(data_rate) | BV(HSMCI_MR_RDPROOF) | BV(HSMCI_MR_WRPROOF);
timer_delay(10);
}
{
(void)hsmci;
- HSMCI_HW_INIT();
- STROBE_INIT();
+ SD_PIN_INIT();
pmc_periphEnable(HSMCI_ID);
HSMCI_CR = BV(HSMCI_CR_SWRST);
HSMCI_DTOR = 0xFF | HSMCI_DTOR_DTOMUL_1048576;
HSMCI_CSTOR = 0xFF | HSMCI_CSTOR_CSTOMUL_1048576;
- HSMCI_MR = HSMCI_CLK_DIV(HSMCI_INIT_SPEED) | ((0x7u << HSMCI_MR_PWSDIV_SHIFT) & HSMCI_MR_PWSDIV_MASK) | BV(HSMCI_MR_RDPROOF);
+ HSMCI_MR = HSMCI_CLK_DIV(HSMCI_INIT_SPEED) | BV(HSMCI_MR_RDPROOF) | BV(HSMCI_MR_WRPROOF);
HSMCI_CFG = BV(HSMCI_CFG_FIFOMODE) | BV(HSMCI_CFG_FERRCTRL);
- sysirq_setHandler(INT_HSMCI, hsmci_irq);
HSMCI_CR = BV(HSMCI_CR_MCIEN);
HSMCI_DMA = 0;
- //init DMAC
- DMAC_EBCIDR = 0x3FFFFF;
- DMAC_CHDR = 0x1F;
-
-
- pmc_periphEnable(DMAC_ID);
- DMAC_EN = BV(DMAC_EN_ENABLE);
- sysirq_setHandler(INT_DMAC, dmac_irq);
-
- DMAC_EBCIER = BV(DMAC_EBCIER_BTC0) | BV(DMAC_EBCIER_ERR0);
+ dmac_enableCh(HSMCI_DMAC_CH, NULL);
}
projects / bertos.git / blobdiff