#include <drv/irq_cm3.h>
#include <drv/clock_stm32.h>
#include <drv/i2c.h>
+#include <drv/timer.h>
#include <io/stm32.h>
struct stm32_i2c *i2c = (struct stm32_i2c *)I2C1_BASE;
+
+#define WAIT_BTF(base) while( !(base->SR1 & BV(SR1_BTF)) )
+#define WAIT_RXE(base) while( !(base->SR1 & BV(SR1_RXE)) )
+
+INLINE uint32_t get_status(struct stm32_i2c *base)
+{
+ return ((base->SR1 | (base->SR2 << 16)) & 0x00FFFFFF);
+}
+
+
+INLINE bool check_i2cStatus(uint32_t event)
+{
+ while (true)
+ {
+ uint32_t stat = get_status(i2c);
+
+ if (stat == event)
+ break;
+
+ if (stat & SR1_ERR_MASK)
+ {
+ LOG_ERR("[%08lx]\n", stat & SR1_ERR_MASK);
+ i2c->SR1 &= ~SR1_ERR_MASK;
+
+ i2c->CR1 |= CR1_START_SET;
+ return false;
+ }
+
+ }
+
+ return true;
+}
+
/**
* Send START condition on the bus.
*
*/
static bool i2c_builtin_start(void)
{
+
+ i2c->CR1 |= (CR1_ACK_SET | BV(CR1_POS) | CR1_PE_SET);
+
i2c->CR1 |= CR1_START_SET;
- return ((i2c->SR1 & (BV(SR1_BUSY) | BV(SR1_MSL))) &
- (i2c->SR2 & BV(SR2_SB)));
+ if(check_i2cStatus(I2C_EVENT_MASTER_MODE_SELECT))
+ return true;
+
+ return false;
}
*/
bool i2c_builtin_start_w(uint8_t id)
{
- id &= OAR1_ADD0_RESET;
+
+ /*
+ * Loop on the select write sequence: when the eeprom is busy
+ * writing previously sent data it will reply to the SLA_W
+ * control byte with a NACK. In this case, we must
+ * keep trying until the eeprom responds with an ACK.
+ */
+ ticks_t start = timer_clock();
while (i2c_builtin_start())
{
+ i2c->DR = id & OAR1_ADD0_RESET;
+
+ if(check_i2cStatus(I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED))
+ return true;
+
+ if (timer_clock() - start > ms_to_ticks(CONFIG_I2C_START_TIMEOUT))
+ {
+ LOG_ERR("Timeout on I2C_START\n");
+ break;
+ }
}
+
return false;
}
*/
bool i2c_builtin_start_r(uint8_t id)
{
+ i2c_builtin_start();
+
+ i2c->DR = (id | OAR1_ADD0_SET);
+
+ if(check_i2cStatus(I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED))
+ return true;
- id |= OAR1_ADD0_SET;
return false;
}
void i2c_builtin_stop(void)
{
i2c->CR1 |= CR1_STOP_SET;
+ i2c->CR1 &= CR1_PE_RESET;
}
-/**
- * Put a single byte in master transmitter mode
- * to the selected slave device through the TWI bus.
- *
- * \return true on success, false on error.
- */
+
bool i2c_builtin_put(const uint8_t data)
{
-
return true;
}
-/**
- * Get 1 byte from slave in master transmitter mode
- * to the selected slave device through the TWI bus.
- * If \a ack is true issue a ACK after getting the byte,
- * otherwise a NACK is issued.
- *
- * \return the byte read if ok, EOF on errors.
- */
int i2c_builtin_get(bool ack)
{
return 0;
}
+bool i2c_send(const void *_buf, size_t count)
+{
+ const uint8_t *buf = (const uint8_t *)_buf;
+
+ i2c->DR = *buf++;
+ count--;
+
+
+ while (count)
+ {
+ ASSERT(buf);
+ WAIT_BTF(i2c);
+
+ i2c->DR = *buf++;
+ count--;
+
+ }
+
+ if(check_i2cStatus(I2C_EVENT_MASTER_BYTE_TRANSMITTED))
+ return true;
+
+ return false;
+}
+
+/**
+ * In order to read bytes from the i2c we should make some tricks.
+ * This because the silicon manage automatically the NACK on last byte, so to read
+ * one, two or three byte we should manage separately these cases.
+ */
+bool i2c_recv(void *_buf, size_t count)
+{
+ uint8_t *buf = (uint8_t *)_buf;
+
+ while (count)
+ {
+ if (count == 1)
+ {
+ i2c->CR1 &= ~BV(CR1_POS);
+
+ if(!check_i2cStatus(I2C_EVENT_MASTER_BYTE_RECEIVED))
+ return false;
+
+ i2c->CR1 &= CR1_ACK_RESET;
+
+ *buf++ = i2c->DR;
+ count = 0;
+ }
+ else if (count == 2)
+ {
+ i2c->CR1 &= CR1_ACK_RESET;
+
+ WAIT_BTF(i2c);
+
+ i2c->CR1 |= CR1_STOP_SET;
+
+ *buf++ = i2c->DR;
+ *buf++ = i2c->DR;
+
+ count = 0;
+
+ i2c->CR1 &= ~BV(CR1_POS);
+
+ }
+ else if (count == 3)
+ {
+ i2c->CR1 &= ~BV(CR1_POS);
+
+ WAIT_BTF(i2c);
+
+ i2c->CR1 &= CR1_ACK_RESET;
+
+ *buf++ = i2c->DR;
+
+ i2c->CR1 |= CR1_STOP_SET;
+
+ *buf++ = i2c->DR;
+
+ WAIT_RXE(i2c);
+
+ *buf++ = i2c->DR;
+
+ count = 0;
+ }
+ else
+ {
+ i2c->CR1 &= ~BV(CR1_POS);
+
+ WAIT_BTF(i2c);
+
+ *buf++ = i2c->DR;
+
+ count--;
+ }
+ }
+
+ return true;
+}
+
MOD_DEFINE(i2c);
/**
RCC->APB2ENR |= RCC_APB2_GPIOB;
RCC->APB1ENR |= RCC_APB1_I2C1;
+ /* Set gpio to use I2C driver */
stm32_gpioPinConfig((struct stm32_gpio *)GPIOB_BASE, GPIO_I2C1_SCL_PIN,
GPIO_MODE_AF_OD, GPIO_SPEED_50MHZ);
stm32_gpioPinConfig((struct stm32_gpio *)GPIOB_BASE, GPIO_I2C1_SDA_PIN,
GPIO_MODE_AF_OD, GPIO_SPEED_50MHZ);
+
+ /* Clear all needed registers */
i2c->CR1 = 0;
i2c->CR2 = 0;
i2c->CCR = 0;
i2c->TRISE = 0;
i2c->OAR1 = 0;
+ /* Set PCLK1 frequency accornding to the master clock settings. See stm32_clock.c */
i2c->CR2 |= CR2_FREQ_36MHZ;
/* Configure spi in standard mode */
#if CONFIG_I2C_FREQ <= 100000
+ i2c->CCR |= (uint16_t)((CR2_FREQ_36MHZ * 1000000) / (CONFIG_I2C_FREQ << 1));
i2c->TRISE |= (CR2_FREQ_36MHZ + 1);
- i2c->CCR |= 4;
#else
#error fast mode not supported
#endif
- i2c->CR1 |= CR1_PE_SET;
- i2c->CR1 |= CR1_ACK_SET;
}
projects / bertos.git / blobdiff