*/
+
+#include "hw/hw_i2s.h"
+
#include "cfg/cfg_i2s.h"
// Define log settings for cfg/log.h.
DmacDesc *next;
DmacDesc *prev;
-static uint8_t *sample_buff;
+bool error = false;
+uint32_t cfg;
+uint32_t ctrla;
+uint32_t ctrlb;
+
+static int16_t *sample_buff;
static size_t next_idx = 0;
static size_t chunk_size = 0;
static size_t remaing_size = 0;
+static size_t transfer_size = 0;
static bool single_transfer;
-static uint32_t cfg;
-static uint32_t ctrla;
-static uint32_t ctrlb;
-
-
static void sam3_i2s_txStop(I2s *i2s)
{
(void)i2s;
static void sam3_i2s_txWait(I2s *i2s)
{
(void)i2s;
+ event_wait(&data_ready);
}
-static void i2s_dmac_irq(void)
+static void i2s_dmac_irq(uint32_t status)
{
+ I2S_STROBE_ON();
if (single_transfer)
{
single_transfer = false;
}
else
{
- prev = curr;
- curr = next;
- next = prev;
-
- dmac_setSourcesLLI(I2S_DMAC_CH, curr, (uint32_t)&sample_buff[next_idx], (uint32_t)&SSC_THR, (uint32_t)next);
- dmac_configureDmacLLI(I2S_DMAC_CH, curr, chunk_size / 2, cfg, ctrla, ctrlb);
-
- event_do(&data_ready);
+ if (status & (BV(I2S_DMAC_CH) << DMAC_EBCIDR_ERR0))
+ {
+ error = true;
+ // Disable to reset channel and clear fifo
+ DMAC_CHDR = BV(I2S_DMAC_CH);
+ }
+ else
+ {
+ prev = curr;
+ curr = next;
+ next = prev;
+
+ curr->src_addr = (uint32_t)&sample_buff[next_idx];
+ curr->dst_addr = (uint32_t)&SSC_THR;
+ curr->dsc_addr = (uint32_t)next;
+ curr->ctrla = ctrla | (chunk_size & 0xffff);
+ curr->ctrlb = ctrlb & ~BV(DMAC_CTRLB_IEN);
+
+ remaing_size -= chunk_size;
+ next_idx += chunk_size;
+
+ if (remaing_size <= 0)
+ {
+ remaing_size = transfer_size;
+ next_idx = 0;
+ }
+ }
}
+ event_do(&data_ready);
+ I2S_STROBE_OFF();
}
static void sam3_i2s_txStart(I2s *i2s, void *buf, size_t len, size_t slice_len)
i2s->hw->end = false;
single_transfer = false;
- sample_buff = (uint8_t *)buf;
+ sample_buff = (int16_t *)buf;
next_idx = 0;
- chunk_size = slice_len;
- remaing_size = len;
+ chunk_size = slice_len / 2;
+ remaing_size = len / 2;
+ transfer_size = len / 2;
+
//Confing DMAC
- uint32_t cfg = BV(DMAC_CFG_DST_H2SEL) |
- ((3 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | (3 & DMAC_CFG_SRC_PER_MASK);
- uint32_t ctrla = DMAC_CTRLA_SRC_WIDTH_HALF_WORD | DMAC_CTRLA_DST_WIDTH_HALF_WORD;
- uint32_t ctrlb = BV(DMAC_CTRLB_SRC_DSCR) |
- DMAC_CTRLB_FC_MEM2PER_DMA_FC |
- DMAC_CTRLB_DST_INCR_FIXED | DMAC_CTRLB_SRC_INCR_INCREMENTING;
+ DMAC_CHDR = BV(I2S_DMAC_CH);
+ reg32_t reg = DMAC_EBCISR;
+ LOG_INFO("Start streaming [%08lx]\n", reg);
- /* Program the dma with the first and second chunk of samples and update counter */
- i2s->ctx.tx_callback(i2s, &sample_buff[0], chunk_size);
+ cfg = BV(DMAC_CFG_DST_H2SEL) | BV(DMAC_CFG_SOD) |
+ ((3 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | (3 & DMAC_CFG_SRC_PER_MASK);
+ ctrla = DMAC_CTRLA_SRC_WIDTH_HALF_WORD | DMAC_CTRLA_DST_WIDTH_HALF_WORD;
+ ctrlb = DMAC_CTRLB_FC_MEM2PER_DMA_FC | DMAC_CTRLB_DST_INCR_FIXED | DMAC_CTRLB_SRC_INCR_INCREMENTING;
- curr = &lli0;
prev = &lli0;
+ curr = &lli0;
next = &lli1;
- dmac_setSourcesLLI(I2S_DMAC_CH, curr, (uint32_t)&sample_buff[0], (uint32_t)&SSC_THR,(uint32_t)next);
- dmac_configureDmacLLI(I2S_DMAC_CH, curr, chunk_size / 2, cfg, ctrla, ctrlb);
+ i2s->ctx.tx_callback(i2s, &sample_buff[0], chunk_size * 2);
+
+ lli0.src_addr = (uint32_t)&sample_buff[0];
+ lli0.dst_addr = (uint32_t)&SSC_THR;
+ lli0.dsc_addr = (uint32_t)next;
+ lli0.ctrla = ctrla | (chunk_size & 0xffff);
+ lli0.ctrlb = ctrlb & ~BV(DMAC_CTRLB_IEN);
remaing_size -= chunk_size;
next_idx += chunk_size;
if (chunk_size <= remaing_size)
{
- i2s->ctx.tx_callback(i2s, &sample_buff[next_idx], chunk_size);
+ i2s->ctx.tx_callback(i2s, &sample_buff[next_idx], chunk_size * 2);
prev = curr;
curr = next;
next = prev;
- dmac_setSourcesLLI(I2S_DMAC_CH, curr, (uint32_t)&sample_buff[next_idx], (uint32_t)&SSC_THR,(uint32_t)next);
- dmac_configureDmacLLI(I2S_DMAC_CH, curr, chunk_size / 2, cfg, ctrla, ctrlb);
+ lli1.src_addr = (uint32_t)&sample_buff[next_idx];
+ lli1.dst_addr = (uint32_t)&SSC_THR;
+ lli1.dsc_addr = (uint32_t)next;
+ lli1.ctrla = ctrla | (chunk_size & 0xffff);
+ lli1.ctrlb = ctrlb & ~BV(DMAC_CTRLB_IEN);
remaing_size -= chunk_size;
next_idx += chunk_size;
}
+ dmac_setLLITransfer(I2S_DMAC_CH, &lli0, cfg);
+
if (dmac_start(I2S_DMAC_CH) < 0)
- kprintf("start erros[%x]\n", dmac_error(I2S_DMAC_CH));
+ {
+ LOG_ERR("DMAC start[%x]\n", dmac_error(I2S_DMAC_CH));
+ return;
+ }
+ error = false;
SSC_CR = BV(SSC_TXEN);
+ I2S_STROBE_OFF();
while (1)
{
event_wait(&data_ready);
- if (i2s->hw->end)
- break;
-
- remaing_size -= chunk_size;
- next_idx += chunk_size;
-
- if (remaing_size <= 0)
+ if (error)
{
- remaing_size = len;
- next_idx = 0;
+ LOG_ERR("Errow while streaming.\n");
+ break;
}
- if (dmac_start(I2S_DMAC_CH) < 0)
- kprintf("start erros[%x]\n", dmac_error(I2S_DMAC_CH));
+ if (i2s->hw->end)
+ break;
- i2s->ctx.tx_callback(i2s, &sample_buff[next_idx], chunk_size);
+ i2s->ctx.tx_callback(i2s, &sample_buff[next_idx], chunk_size * 2);
+ cpu_relax();
}
}
static bool sam3_i2s_isRxFinish(struct I2s *i2s)
{
(void)i2s;
- return dmac_isDone(I2S_DMAC_CH);
+ return 0;
}
static void sam3_i2s_txBuf(struct I2s *i2s, void *buf, size_t len)
static int sam3_i2s_write(struct I2s *i2s, uint32_t sample)
{
(void)i2s;
+
SSC_CR = BV(SSC_TXEN);
- while(!(SSC_SR & BV(SSC_TXRDY)));
+ while(!(SSC_SR & BV(SSC_TXRDY)))
+ cpu_relax();
+
SSC_THR = sample;
return 0;
}
static uint32_t sam3_i2s_read(struct I2s *i2s)
{
(void)i2s;
- SSC_CR = BV(SSC_RXEN);
- while(!(SSC_SR & BV(SSC_RXRDY)));
- return SSC_RHR;
-}
+ SSC_CR = BV(SSC_RXEN);
+ while(!(SSC_SR & BV(SSC_RXRDY)))
+ cpu_relax();
-static DECLARE_ISR(irq_ssc)
-{
+ return SSC_RHR;
}
-
-
/* We divite for 2 because the min clock for i2s i MCLK/2 */
#define MCK_DIV (CPU_FREQ / (CONFIG_SAMPLE_FREQ * CONFIG_WORD_BIT_SIZE * CONFIG_CHANNEL_NUM * 2))
#define DATALEN ((CONFIG_WORD_BIT_SIZE - 1) & SSC_DATLEN_MASK)
DB(i2s->ctx._type = I2S_SAM3X;)
i2s->hw = &i2s_hw;
+ I2S_STROBE_INIT();
+
PIOA_PDR = BV(SSC_TK) | BV(SSC_TF) | BV(SSC_TD);
PIO_PERIPH_SEL(PIOA_BASE, BV(SSC_TK) | BV(SSC_TF) | BV(SSC_TD), PIO_PERIPH_B);
PIOB_PDR = BV(SSC_RD) | BV(SSC_RF);
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