#include <string.h>
-#define I2S_DMAC_CH 3
+#define I2S_DMAC_CH 0
#define I2S_CACHED_CHUNK_SIZE 2
((3 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | \
(4 & DMAC_CFG_SRC_PER_MASK))
+#define I2S_TX_DMAC_CTRLB (DMAC_CTRLB_FC_MEM2PER_DMA_FC | \
+ DMAC_CTRLB_DST_INCR_FIXED | \
+ DMAC_CTRLB_SRC_INCR_INCREMENTING)
+
+
+#define I2S_RX_DMAC_CFG (BV(DMAC_CFG_SRC_H2SEL) | \
+ BV(DMAC_CFG_SOD) | \
+ ((3 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | \
+ (4 & DMAC_CFG_SRC_PER_MASK))
+
+#define I2S_RX_DMAC_CTRLB (DMAC_CTRLB_FC_PER2MEM_DMA_FC | \
+ DMAC_CTRLB_DST_INCR_INCREMENTING | \
+ DMAC_CTRLB_SRC_INCR_FIXED)
+
#if CONFIG_WORD_BIT_SIZE == 32
#define I2S_TX_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_WORD | \
#define I2S_TX_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_HALF_WORD | \
DMAC_CTRLA_DST_WIDTH_HALF_WORD)
#define I2S_RX_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_HALF_WORD | \
- DMAC_CTRLA_DST_WIDTH_HALF_WORD)
+ DMAC_CTRLA_DST_WIDTH_HALF_WORD)
#define I2S_WORD_BYTE_SIZE 2
#elif CONFIG_WORD_BIT_SIZE == 8
#define I2S_TX_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_BYTE | \
DMAC_CTRLA_DST_WIDTH_BYTE)
#define I2S_RX_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_BYTE | \
- DMAC_CTRLA_DST_WIDTH_HALF_WORD)
+ DMAC_CTRLA_DST_WIDTH_BYTE)
#define I2S_WORD_BYTE_SIZE 1
#else
#endif
-#define I2S_TX_DMAC_CTRLB (DMAC_CTRLB_FC_MEM2PER_DMA_FC | \
- DMAC_CTRLB_DST_INCR_FIXED | \
- DMAC_CTRLB_SRC_INCR_INCREMENTING)
-
-#define I2S_RX_DMAC_CFG (BV(DMAC_CFG_SRC_H2SEL) | \
- BV(DMAC_CFG_SOD) | \
- ((4 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | \
- (4 & DMAC_CFG_SRC_PER_MASK))
-
-#define I2S_RX_DMAC_CTRLB (DMAC_CTRLB_FC_PER2MEM_DMA_FC | \
- DMAC_CTRLB_DST_INCR_INCREMENTING | \
- DMAC_CTRLB_SRC_INCR_FIXED)
-
-
-
#define I2S_STATUS_ERR BV(0)
#define I2S_STATUS_SINGLE_TRASF BV(1)
#define I2S_STATUS_TX BV(2)
-#define I2S_STATUS_RX BV(3)
-struct I2sHardware
-{
- bool end;
-};
+#define I2S_STATUS_END_TX BV(3)
+#define I2S_STATUS_RX BV(4)
+#define I2S_STATUS_END_RX BV(5)
+
-struct I2sHardware i2s_hw;
static Event data_ready;
DmacDesc lli0;
static uint8_t *sample_buff;
static size_t next_idx = 0;
static size_t chunk_size = 0;
-static size_t remaing_size = 0;
static size_t transfer_size = 0;
static void sam3_i2s_txStop(I2s *i2s)
SSC_CR = BV(SSC_TXDIS);
dmac_stop(I2S_DMAC_CH);
- i2s->hw->end = true;
- remaing_size = 0;
next_idx = 0;
transfer_size = 0;
+ i2s_status |= I2S_STATUS_END_TX;
i2s_status &= ~I2S_STATUS_TX;
-
event_do(&data_ready);
}
static void i2s_dmac_irq(uint32_t status)
{
- I2S_STROBE_ON();
if (i2s_status & I2S_STATUS_SINGLE_TRASF)
{
i2s_status &= ~I2S_STATUS_SINGLE_TRASF;
curr->ctrlb = I2S_RX_DMAC_CTRLB & ~BV(DMAC_CTRLB_IEN);
}
- remaing_size -= chunk_size;
- next_idx += chunk_size;
-
- if (remaing_size <= 0)
- {
- remaing_size = transfer_size;
- next_idx = 0;
- }
}
}
event_do(&data_ready);
- I2S_STROBE_OFF();
}
ASSERT(len >= slice_len);
ASSERT(!(len % slice_len));
- i2s->hw->end = false;
- i2s_status &= ~I2S_STATUS_SINGLE_TRASF;
+ i2s_status &= ~(I2S_STATUS_END_TX | I2S_STATUS_SINGLE_TRASF);
sample_buff = (uint8_t *)buf;
next_idx = 0;
chunk_size = slice_len;
- remaing_size = len;
+ size_t remaing_size = len;
transfer_size = len;
remaing_size -= chunk_size;
next_idx += chunk_size;
- if (chunk_size > remaing_size)
- break;
-
+ if (remaing_size <= 0)
+ {
+ remaing_size = transfer_size;
+ next_idx = 0;
+ }
}
dmac_setLLITransfer(I2S_DMAC_CH, prev, I2S_TX_DMAC_CFG);
i2s_status |= I2S_STATUS_TX;
SSC_CR = BV(SSC_TXEN);
- I2S_STROBE_OFF();
while (1)
{
event_wait(&data_ready);
+ I2S_STROBE_ON();
+ remaing_size -= chunk_size;
+ next_idx += chunk_size;
+
+ if (remaing_size <= 0)
+ {
+ remaing_size = transfer_size;
+ next_idx = 0;
+ }
+
if (i2s_status & I2S_STATUS_ERR)
{
LOG_ERR("Error while streaming.\n");
break;
}
- if (i2s->hw->end)
+ if (i2s_status & I2S_STATUS_END_TX)
{
LOG_INFO("Stop streaming.\n");
break;
}
i2s->ctx.tx_callback(i2s, &sample_buff[next_idx], chunk_size);
- cpu_relax();
+ I2S_STROBE_OFF();
}
}
SSC_CR = BV(SSC_RXDIS) | BV(SSC_TXDIS);
dmac_stop(I2S_DMAC_CH);
- i2s->hw->end = true;
- remaing_size = 0;
+ i2s_status |= I2S_STATUS_END_RX;
next_idx = 0;
transfer_size = 0;
ASSERT(len >= slice_len);
ASSERT(!(len % slice_len));
- i2s->hw->end = false;
- i2s_status &= ~I2S_STATUS_SINGLE_TRASF;
+ i2s_status &= ~(I2S_STATUS_END_RX | I2S_STATUS_SINGLE_TRASF);
sample_buff = (uint8_t *)buf;
next_idx = 0;
chunk_size = slice_len;
- remaing_size = len;
+ size_t remaing_size = len;
transfer_size = len;
memset(&lli0, 0, sizeof(DmacDesc));
curr = next;
next = prev;
- i2s->ctx.rx_callback(i2s, &sample_buff[next_idx], chunk_size);
curr->src_addr = (uint32_t)&SSC_RHR;
curr->dst_addr = (uint32_t)&sample_buff[next_idx];
curr->dsc_addr = (uint32_t)next;
remaing_size -= chunk_size;
next_idx += chunk_size;
- if (chunk_size > remaing_size)
- break;
-
+ if (remaing_size <= 0)
+ {
+ remaing_size = transfer_size;
+ next_idx = 0;
+ }
}
+
dmac_setLLITransfer(I2S_DMAC_CH, prev, I2S_RX_DMAC_CFG);
if (dmac_start(I2S_DMAC_CH) < 0)
i2s_status &= ~I2S_STATUS_ERR;
i2s_status |= I2S_STATUS_RX;
- SSC_CR = BV(SSC_RXEN) | BV(SSC_TXEN);
- I2S_STROBE_OFF();
+ SSC_CR = BV(SSC_TXEN) | BV(SSC_RXEN);
while (1)
{
event_wait(&data_ready);
+ I2S_STROBE_ON();
+ i2s->ctx.rx_callback(i2s, &sample_buff[next_idx], chunk_size);
+
+ remaing_size -= chunk_size;
+ next_idx += chunk_size;
+
+ if (remaing_size <= 0)
+ {
+ remaing_size = transfer_size;
+ next_idx = 0;
+ }
+
if (i2s_status & I2S_STATUS_ERR)
{
LOG_ERR("Error while streaming.\n");
break;
}
- if (i2s->hw->end)
+ if (i2s_status & I2S_STATUS_END_RX)
{
LOG_INFO("Stop streaming.\n");
break;
}
- i2s->ctx.rx_callback(i2s, &sample_buff[next_idx], chunk_size);
- cpu_relax();
+ I2S_STROBE_OFF();
}
}
static bool sam3_i2s_isTxFinish(struct I2s *i2s)
{
- return i2s->hw->end;
+ (void)i2s;
+ return (i2s_status & I2S_STATUS_END_TX);
}
static bool sam3_i2s_isRxFinish(struct I2s *i2s)
{
- return i2s->hw->end;
+ (void)i2s;
+ return (i2s_status & I2S_STATUS_END_RX);
}
static void sam3_i2s_txBuf(struct I2s *i2s, void *buf, size_t len)
dmac_configureDmac(I2S_DMAC_CH, len / I2S_WORD_BYTE_SIZE, I2S_RX_DMAC_CFG, I2S_RX_DMAC_CTRLA, I2S_RX_DMAC_CTRLB);
dmac_start(I2S_DMAC_CH);
- SSC_CR = BV(SSC_RXEN);
+ SSC_CR = BV(SSC_TXEN) | BV(SSC_RXEN);
}
static int sam3_i2s_write(struct I2s *i2s, uint32_t sample)
i2s->ctx.rx_stop = sam3_i2s_rxStop;
DB(i2s->ctx._type = I2S_SAM3X;)
- i2s->hw = &i2s_hw;
I2S_STROBE_INIT();