*/
+
+#include "hw/hw_i2s.h"
+
#include "cfg/cfg_i2s.h"
// Define log settings for cfg/log.h.
#include <io/cm3.h>
+#include <string.h>
-#define I2S_DMAC_CH 1
-struct I2sHardware
-{
- bool end;
-};
+#define I2S_DMAC_CH 0
+#define I2S_CACHED_CHUNK_SIZE 2
-struct I2sHardware i2s_hw;
-static Event data_ready;
-/* We divite for 2 because the min clock for i2s i MCLK/2 */
-#define MCK_DIV (CPU_FREQ / (48000 * CONFIG_WORD_BIT_SIZE * CONFIG_CHANNEL_NUM * 2))
-#define DATALEN ((CONFIG_WORD_BIT_SIZE - 1) & SSC_DATLEN_MASK)
-#define DELAY ((CONFIG_DELAY << SSC_STTDLY_SHIFT) & SSC_STTDLY_MASK)
-#define PERIOD ((CONFIG_PERIOD << (SSC_PERIOD_SHIFT)) & SSC_PERIOD_MASK)
-#define DATNB ((CONFIG_WORD_PER_FRAME << SSC_DATNB_SHIFT) & SSC_DATNB_MASK)
-#define FSLEN ((CONFIG_FRAME_SYNC_SIZE << SSC_FSLEN_SHIFT) & SSC_FSLEN_MASK)
-#define EXTRA_FSLEN (CONFIG_EXTRA_FRAME_SYNC_SIZE << SSC_FSLEN_EXT)
+#define I2S_TX_DMAC_CFG (BV(DMAC_CFG_DST_H2SEL) | \
+ BV(DMAC_CFG_SOD) | \
+ ((3 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | \
+ (4 & DMAC_CFG_SRC_PER_MASK))
+
+#define I2S_TX_DMAC_CTRLB (DMAC_CTRLB_FC_MEM2PER_DMA_FC | \
+ DMAC_CTRLB_DST_INCR_FIXED | \
+ DMAC_CTRLB_SRC_INCR_INCREMENTING)
+
+
+#define I2S_RX_DMAC_CFG (BV(DMAC_CFG_SRC_H2SEL) | \
+ BV(DMAC_CFG_SOD) | \
+ ((3 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | \
+ (4 & DMAC_CFG_SRC_PER_MASK))
+
+#define I2S_RX_DMAC_CTRLB (DMAC_CTRLB_FC_PER2MEM_DMA_FC | \
+ DMAC_CTRLB_DST_INCR_INCREMENTING | \
+ DMAC_CTRLB_SRC_INCR_FIXED)
+
+
+#if CONFIG_WORD_BIT_SIZE == 32
+ #define I2S_TX_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_WORD | \
+ DMAC_CTRLA_DST_WIDTH_WORD)
+ #define I2S_RX_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_WORD | \
+ DMAC_CTRLA_DST_WIDTH_WORD)
+ #define I2S_WORD_BYTE_SIZE 4
+#elif CONFIG_WORD_BIT_SIZE == 16
+
+ #define I2S_TX_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_HALF_WORD | \
+ DMAC_CTRLA_DST_WIDTH_HALF_WORD)
+ #define I2S_RX_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_HALF_WORD | \
+ DMAC_CTRLA_DST_WIDTH_HALF_WORD)
+ #define I2S_WORD_BYTE_SIZE 2
+#elif CONFIG_WORD_BIT_SIZE == 8
+
+ #define I2S_TX_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_BYTE | \
+ DMAC_CTRLA_DST_WIDTH_BYTE)
+ #define I2S_RX_DMAC_CTRLA (DMAC_CTRLA_SRC_WIDTH_BYTE | \
+ DMAC_CTRLA_DST_WIDTH_BYTE)
+ #define I2S_WORD_BYTE_SIZE 1
+
+#else
+ #error Wrong i2s word size.
+#endif
+
+
+#define I2S_STATUS_ERR BV(0)
+#define I2S_STATUS_SINGLE_TRASF BV(1)
+#define I2S_STATUS_TX BV(2)
+#define I2S_STATUS_END_TX BV(3)
+#define I2S_STATUS_RX BV(4)
+#define I2S_STATUS_END_RX BV(5)
+
+
+static Event data_ready;
DmacDesc lli0;
DmacDesc lli1;
DmacDesc *next;
DmacDesc *prev;
+static uint8_t i2s_status;
static uint8_t *sample_buff;
static size_t next_idx = 0;
static size_t chunk_size = 0;
-static size_t remaing_size = 0;
-
-static uint32_t cfg;
-static uint32_t ctrla;
-static uint32_t ctrlb;
-
+static size_t transfer_size = 0;
static void sam3_i2s_txStop(I2s *i2s)
{
SSC_CR = BV(SSC_TXDIS);
dmac_stop(I2S_DMAC_CH);
- i2s->hw->end = true;
- remaing_size = 0;
- kprintf("stop\n");
+ next_idx = 0;
+ transfer_size = 0;
+ i2s_status |= I2S_STATUS_END_TX;
+ i2s_status &= ~I2S_STATUS_TX;
event_do(&data_ready);
}
static void sam3_i2s_txWait(I2s *i2s)
{
(void)i2s;
+ event_wait(&data_ready);
}
-static void i2s_dmac_irq(void)
+static void i2s_dmac_irq(uint32_t status)
{
- prev = curr;
- curr = next;
- next = prev;
-
- dmac_setSourcesLLI(I2S_DMAC_CH, curr, (uint32_t)&sample_buff[next_idx], (uint32_t)&SSC_THR, (uint32_t)next);
- dmac_configureDmacLLI(I2S_DMAC_CH, curr, chunk_size / 2, cfg, ctrla, ctrlb);
+ if (i2s_status & I2S_STATUS_SINGLE_TRASF)
+ {
+ i2s_status &= ~I2S_STATUS_SINGLE_TRASF;
+ }
+ else
+ {
+ if (status & (BV(I2S_DMAC_CH) << DMAC_EBCIDR_ERR0))
+ {
+ i2s_status |= I2S_STATUS_ERR;
+ // Disable to reset channel and clear fifo
+ dmac_stop(I2S_DMAC_CH);
+ }
+ else
+ {
+ prev = curr;
+ curr = next;
+ next = prev;
+
+ if (i2s_status & I2S_STATUS_TX)
+ {
+ curr->src_addr = (uint32_t)&sample_buff[next_idx];
+ curr->dst_addr = (uint32_t)&SSC_THR;
+ curr->dsc_addr = (uint32_t)next;
+ curr->ctrla = I2S_TX_DMAC_CTRLA | ((chunk_size / I2S_WORD_BYTE_SIZE) & 0xffff);
+ curr->ctrlb = I2S_TX_DMAC_CTRLB & ~BV(DMAC_CTRLB_IEN);
+ }
+ else
+ {
+ curr->src_addr = (uint32_t)&SSC_RHR;
+ curr->dst_addr = (uint32_t)&sample_buff[next_idx];
+ curr->dsc_addr = (uint32_t)next;
+ curr->ctrla = I2S_RX_DMAC_CTRLA | ((chunk_size / I2S_WORD_BYTE_SIZE) & 0xffff);
+ curr->ctrlb = I2S_RX_DMAC_CTRLB & ~BV(DMAC_CTRLB_IEN);
+ }
+ }
+ }
event_do(&data_ready);
}
+
static void sam3_i2s_txStart(I2s *i2s, void *buf, size_t len, size_t slice_len)
{
ASSERT(buf);
ASSERT(len >= slice_len);
ASSERT(!(len % slice_len));
- i2s->hw->end = false;
+ i2s_status &= ~(I2S_STATUS_END_TX | I2S_STATUS_SINGLE_TRASF);
sample_buff = (uint8_t *)buf;
next_idx = 0;
chunk_size = slice_len;
- remaing_size = len;
-
- //Confing DMAC
- uint32_t cfg = BV(DMAC_CFG_DST_H2SEL) |
- ((3 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | (3 & DMAC_CFG_SRC_PER_MASK);
- uint32_t ctrla = DMAC_CTRLA_SRC_WIDTH_HALF_WORD | DMAC_CTRLA_DST_WIDTH_HALF_WORD;
- uint32_t ctrlb = BV(DMAC_CTRLB_SRC_DSCR) |
- DMAC_CTRLB_FC_MEM2PER_DMA_FC |
- DMAC_CTRLB_DST_INCR_FIXED | DMAC_CTRLB_SRC_INCR_INCREMENTING;
-
-
- /* Program the dma with the first and second chunk of samples and update counter */
- i2s->ctx.tx_callback(i2s, &sample_buff[0], chunk_size);
+ size_t remaing_size = len;
+ transfer_size = len;
- curr = &lli0;
- prev = &lli0;
- next = &lli1;
- dmac_setSourcesLLI(I2S_DMAC_CH, curr, (uint32_t)&sample_buff[0], (uint32_t)&SSC_THR,(uint32_t)next);
- dmac_configureDmacLLI(I2S_DMAC_CH, curr, chunk_size / 2, cfg, ctrla, ctrlb);
+ memset(&lli0, 0, sizeof(DmacDesc));
+ memset(&lli1, 0, sizeof(DmacDesc));
- remaing_size -= chunk_size;
- next_idx += chunk_size;
+ prev = 0;
+ curr = &lli1;
+ next = &lli0;
- if (chunk_size <= remaing_size)
+ for (int i = 0; i < I2S_CACHED_CHUNK_SIZE; i++)
{
- i2s->ctx.tx_callback(i2s, &sample_buff[next_idx], chunk_size);
-
prev = curr;
curr = next;
next = prev;
- dmac_setSourcesLLI(I2S_DMAC_CH, curr, (uint32_t)&sample_buff[next_idx], (uint32_t)&SSC_THR,(uint32_t)next);
- dmac_configureDmacLLI(I2S_DMAC_CH, curr, chunk_size / 2, cfg, ctrla, ctrlb);
+ i2s->ctx.tx_callback(i2s, &sample_buff[next_idx], chunk_size);
+
+ curr->src_addr = (uint32_t)&sample_buff[next_idx];
+ curr->dst_addr = (uint32_t)&SSC_THR;
+ curr->dsc_addr = (uint32_t)next;
+ curr->ctrla = I2S_TX_DMAC_CTRLA | ((chunk_size / I2S_WORD_BYTE_SIZE) & 0xffff);
+ curr->ctrlb = I2S_TX_DMAC_CTRLB & ~BV(DMAC_CTRLB_IEN);
remaing_size -= chunk_size;
next_idx += chunk_size;
+
+ if (remaing_size <= 0)
+ {
+ remaing_size = transfer_size;
+ next_idx = 0;
+ }
}
+ dmac_setLLITransfer(I2S_DMAC_CH, prev, I2S_TX_DMAC_CFG);
+
if (dmac_start(I2S_DMAC_CH) < 0)
- kprintf("start erros[%x]\n", dmac_error(I2S_DMAC_CH));
+ {
+ LOG_ERR("DMAC start[%x]\n", dmac_error(I2S_DMAC_CH));
+ return;
+ }
+
+ i2s_status &= ~I2S_STATUS_ERR;
+ i2s_status |= I2S_STATUS_TX;
SSC_CR = BV(SSC_TXEN);
while (1)
{
event_wait(&data_ready);
- if (i2s->hw->end)
- break;
-
+ I2S_STROBE_ON();
remaing_size -= chunk_size;
next_idx += chunk_size;
if (remaing_size <= 0)
{
- remaing_size = len;
+ remaing_size = transfer_size;
next_idx = 0;
}
- if (dmac_start(I2S_DMAC_CH) < 0)
- kprintf("start erros[%x]\n", dmac_error(I2S_DMAC_CH));
+ if (i2s_status & I2S_STATUS_ERR)
+ {
+ LOG_ERR("Error while streaming.\n");
+ break;
+ }
+
+ if (i2s_status & I2S_STATUS_END_TX)
+ {
+ LOG_INFO("Stop streaming.\n");
+ break;
+ }
i2s->ctx.tx_callback(i2s, &sample_buff[next_idx], chunk_size);
+ I2S_STROBE_OFF();
}
}
static void sam3_i2s_rxStop(I2s *i2s)
{
(void)i2s;
- SSC_CR = BV(SSC_TXDIS);
+ SSC_CR = BV(SSC_RXDIS) | BV(SSC_TXDIS);
+ dmac_stop(I2S_DMAC_CH);
+
+ i2s_status |= I2S_STATUS_END_RX;
+ next_idx = 0;
+ transfer_size = 0;
+
+ i2s_status &= ~I2S_STATUS_RX;
+
+ event_do(&data_ready);
}
static void sam3_i2s_rxWait(I2s *i2s)
{
(void)i2s;
+ event_wait(&data_ready);
}
static void sam3_i2s_rxStart(I2s *i2s, void *buf, size_t len, size_t slice_len)
{
- (void)i2s;
- (void)buf;
- (void)len;
- (void)slice_len;
+ ASSERT(buf);
+ ASSERT(len >= slice_len);
+ ASSERT(!(len % slice_len));
+
+ i2s_status &= ~(I2S_STATUS_END_RX | I2S_STATUS_SINGLE_TRASF);
+
+ sample_buff = (uint8_t *)buf;
+ next_idx = 0;
+ chunk_size = slice_len;
+ size_t remaing_size = len;
+ transfer_size = len;
+
+ memset(&lli0, 0, sizeof(DmacDesc));
+ memset(&lli1, 0, sizeof(DmacDesc));
+
+ prev = 0;
+ curr = &lli1;
+ next = &lli0;
+
+ for (int i = 0; i < I2S_CACHED_CHUNK_SIZE; i++)
+ {
+ prev = curr;
+ curr = next;
+ next = prev;
+
+ curr->src_addr = (uint32_t)&SSC_RHR;
+ curr->dst_addr = (uint32_t)&sample_buff[next_idx];
+ curr->dsc_addr = (uint32_t)next;
+ curr->ctrla = I2S_RX_DMAC_CTRLA | ((chunk_size / I2S_WORD_BYTE_SIZE) & 0xffff);
+ curr->ctrlb = I2S_RX_DMAC_CTRLB & ~BV(DMAC_CTRLB_IEN);
+
+ remaing_size -= chunk_size;
+ next_idx += chunk_size;
+
+ if (remaing_size <= 0)
+ {
+ remaing_size = transfer_size;
+ next_idx = 0;
+ }
+ }
+
+ dmac_setLLITransfer(I2S_DMAC_CH, prev, I2S_RX_DMAC_CFG);
+
+ if (dmac_start(I2S_DMAC_CH) < 0)
+ {
+ LOG_ERR("DMAC start[%x]\n", dmac_error(I2S_DMAC_CH));
+ return;
+ }
+
+ i2s_status &= ~I2S_STATUS_ERR;
+ i2s_status |= I2S_STATUS_RX;
+
+ SSC_CR = BV(SSC_TXEN) | BV(SSC_RXEN);
+
+ while (1)
+ {
+ event_wait(&data_ready);
+ I2S_STROBE_ON();
+ i2s->ctx.rx_callback(i2s, &sample_buff[next_idx], chunk_size);
+
+ remaing_size -= chunk_size;
+ next_idx += chunk_size;
+
+ if (remaing_size <= 0)
+ {
+ remaing_size = transfer_size;
+ next_idx = 0;
+ }
+
+ if (i2s_status & I2S_STATUS_ERR)
+ {
+ LOG_ERR("Error while streaming.\n");
+ break;
+ }
+
+ if (i2s_status & I2S_STATUS_END_RX)
+ {
+ LOG_INFO("Stop streaming.\n");
+ break;
+ }
+ I2S_STROBE_OFF();
+ }
}
static bool sam3_i2s_isTxFinish(struct I2s *i2s)
{
(void)i2s;
- return i2s->hw->end;//dmac_isDone(&dmac);
+ return (i2s_status & I2S_STATUS_END_TX);
}
static bool sam3_i2s_isRxFinish(struct I2s *i2s)
{
(void)i2s;
- return dmac_isDone(I2S_DMAC_CH);
+ return (i2s_status & I2S_STATUS_END_RX);
}
static void sam3_i2s_txBuf(struct I2s *i2s, void *buf, size_t len)
{
(void)i2s;
-
- uint32_t cfg = BV(DMAC_CFG_DST_H2SEL) |
- ((3 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | (3 & DMAC_CFG_SRC_PER_MASK);
- uint32_t ctrla = DMAC_CTRLA_SRC_WIDTH_HALF_WORD | DMAC_CTRLA_DST_WIDTH_HALF_WORD;
- uint32_t ctrlb = BV(DMAC_CTRLB_SRC_DSCR) | BV(DMAC_CTRLB_DST_DSCR) |
- DMAC_CTRLB_FC_MEM2PER_DMA_FC |
- DMAC_CTRLB_DST_INCR_FIXED | DMAC_CTRLB_SRC_INCR_INCREMENTING;
+ i2s_status |= I2S_STATUS_SINGLE_TRASF;
dmac_setSources(I2S_DMAC_CH, (uint32_t)buf, (uint32_t)&SSC_THR);
- dmac_configureDmac(I2S_DMAC_CH, len / 2, cfg, ctrla, ctrlb);
+ dmac_configureDmac(I2S_DMAC_CH, len / I2S_WORD_BYTE_SIZE, I2S_TX_DMAC_CFG, I2S_TX_DMAC_CTRLA, I2S_TX_DMAC_CTRLB);
dmac_start(I2S_DMAC_CH);
SSC_CR = BV(SSC_TXEN);
{
(void)i2s;
- uint32_t cfg = BV(DMAC_CFG_SRC_H2SEL) |
- ((4 << DMAC_CFG_DST_PER_SHIFT) & DMAC_CFG_DST_PER_MASK) | (4 & DMAC_CFG_SRC_PER_MASK);
- uint32_t ctrla = DMAC_CTRLA_SRC_WIDTH_HALF_WORD | DMAC_CTRLA_DST_WIDTH_HALF_WORD;
- uint32_t ctrlb = BV(DMAC_CTRLB_SRC_DSCR) | BV(DMAC_CTRLB_DST_DSCR) |
- DMAC_CTRLB_FC_PER2MEM_DMA_FC |
- DMAC_CTRLB_DST_INCR_INCREMENTING | DMAC_CTRLB_SRC_INCR_FIXED;
+ i2s_status |= I2S_STATUS_SINGLE_TRASF;
dmac_setSources(I2S_DMAC_CH, (uint32_t)&SSC_RHR, (uint32_t)buf);
- dmac_configureDmac(I2S_DMAC_CH, len / 2, cfg, ctrla, ctrlb);
+ dmac_configureDmac(I2S_DMAC_CH, len / I2S_WORD_BYTE_SIZE, I2S_RX_DMAC_CFG, I2S_RX_DMAC_CTRLA, I2S_RX_DMAC_CTRLB);
dmac_start(I2S_DMAC_CH);
- SSC_CR = BV(SSC_RXEN);
+ SSC_CR = BV(SSC_TXEN) | BV(SSC_RXEN);
}
static int sam3_i2s_write(struct I2s *i2s, uint32_t sample)
{
(void)i2s;
+
SSC_CR = BV(SSC_TXEN);
- while(!(SSC_SR & BV(SSC_TXRDY)));
+ while(!(SSC_SR & BV(SSC_TXRDY)))
+ cpu_relax();
+
SSC_THR = sample;
return 0;
}
static uint32_t sam3_i2s_read(struct I2s *i2s)
{
(void)i2s;
+
SSC_CR = BV(SSC_RXEN);
- while(!(SSC_SR & BV(SSC_RXRDY)));
+ while(!(SSC_SR & BV(SSC_RXRDY)))
+ cpu_relax();
+
return SSC_RHR;
}
-static DECLARE_ISR(irq_ssc)
-{
-}
+/* We divite for 2 because the min clock for i2s i MCLK/2 */
+#define MCK_DIV (CPU_FREQ / (CONFIG_SAMPLE_FREQ * CONFIG_WORD_BIT_SIZE * CONFIG_CHANNEL_NUM * 2))
+#define DATALEN ((CONFIG_WORD_BIT_SIZE - 1) & SSC_DATLEN_MASK)
+#define DELAY ((CONFIG_DELAY << SSC_STTDLY_SHIFT) & SSC_STTDLY_MASK)
+#define PERIOD ((CONFIG_PERIOD << (SSC_PERIOD_SHIFT)) & SSC_PERIOD_MASK)
+#define DATNB ((CONFIG_WORD_PER_FRAME << SSC_DATNB_SHIFT) & SSC_DATNB_MASK)
+#define FSLEN ((CONFIG_FRAME_SYNC_SIZE << SSC_FSLEN_SHIFT) & SSC_FSLEN_MASK)
+#define EXTRA_FSLEN (CONFIG_EXTRA_FRAME_SYNC_SIZE << SSC_FSLEN_EXT)
void i2s_init(I2s *i2s, int channel)
{
i2s->ctx.rx_stop = sam3_i2s_rxStop;
DB(i2s->ctx._type = I2S_SAM3X;)
- i2s->hw = &i2s_hw;
+
+ I2S_STROBE_INIT();
PIOA_PDR = BV(SSC_TK) | BV(SSC_TF) | BV(SSC_TD);
PIO_PERIPH_SEL(PIOA_BASE, BV(SSC_TK) | BV(SSC_TF) | BV(SSC_TD), PIO_PERIPH_B);
+
PIOB_PDR = BV(SSC_RD) | BV(SSC_RF);
PIO_PERIPH_SEL(PIOB_BASE, BV(SSC_RD) | BV(SSC_RF), PIO_PERIPH_A);
* - MSB
* - Frame sync output selection negative
*/
- SSC_TFMR = DATALEN | DATNB | FSLEN | EXTRA_FSLEN | BV(SSC_MSBF) | SSC_FSOS_POSITIVE;
+ SSC_TFMR = DATALEN | DATNB | FSLEN | EXTRA_FSLEN | BV(SSC_MSBF) | SSC_FSOS_NEGATIVE;
// Receiver should start on TX and take the clock from TK
SSC_RCMR = SSC_CKS_CLK | BV(SSC_CKI) | SSC_CKO_CONT | SSC_CKG_NONE | DELAY | PERIOD | SSC_START_TX;
- SSC_RFMR = DATALEN | DATNB | FSLEN | EXTRA_FSLEN | BV(SSC_MSBF) | SSC_FSOS_POSITIVE;
+ SSC_RFMR = DATALEN | DATNB | FSLEN | EXTRA_FSLEN | BV(SSC_MSBF) | SSC_FSOS_NEGATIVE;
SSC_IDR = 0xFFFFFFFF;
- SSC_CR = BV(SSC_TXDIS) | BV(SSC_RXDIS);
dmac_enableCh(I2S_DMAC_CH, i2s_dmac_irq);
event_initGeneric(&data_ready);
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