lm3s1968: generic UART driver.

[bertos.git] / bertos / cpu / cortex-m3 / drv / kdebug_lm3s.c

diff --git a/bertos/cpu/cortex-m3/drv/kdebug_lm3s.c b/bertos/cpu/cortex-m3/drv/kdebug_lm3s.c
index 65c1dccb46512e36ccc917ee349840dccf6355a7..c76ab8ec974b6f12946afbfe143d74effedd2de3 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/kdebug_lm3s.c
+++ b/bertos/cpu/cortex-m3/drv/kdebug_lm3s.c
@@ -40,73 +40,25 @@
 #include <drv/clock_lm3s.h> /* lm3s_busyWait() */
 #include <drv/gpio_lm3s.h>
 #include <io/lm3s.h>
+#include <drv/ser_lm3s.h>
 #include "kdebug_lm3s.h"
 
-INLINE void uart_disable(size_t base)
-{
-       /* Disable the FIFO */
-       HWREG(base + UART_O_LCRH) &= ~UART_LCRH_FEN;
-       /* Disable the UART */
-       HWREG(base + UART_O_CTL) &=
-               ~(UART_CTL_UARTEN | UART_CTL_TXE | UART_CTL_RXE);
-}
-
-INLINE void uart_enable(size_t base)
-{
-       /* Enable the FIFO */
-       HWREG(base + UART_O_LCRH) |= UART_LCRH_FEN;
-       /* Enable RX, TX, and the UART */
-       HWREG(base + UART_O_CTL) |=
-                       UART_CTL_UARTEN | UART_CTL_TXE | UART_CTL_RXE;
-}
-
-INLINE void uart_config(size_t base, uint32_t baud, reg32_t config)
-{
-       unsigned long div;
-       bool hi_speed;
-
-       if (baud * 16 > CPU_FREQ)
-       {
-               hi_speed = true;
-               baud /= 2;
-       }
-       div = (CPU_FREQ * 8 / baud + 1) / 2;
-
-       uart_disable(base);
-
-       if (hi_speed)
-               HWREG(base + UART_O_CTL) |= UART_CTL_HSE;
-       else
-               HWREG(base + UART_O_CTL) &= ~UART_CTL_HSE;
-
-       /* Set the baud rate */
-       HWREG(base + UART_O_IBRD) = div / 64;
-       HWREG(base + UART_O_FBRD) = div % 64;
-
-       /* Set parity, data length, and number of stop bits. */
-       HWREG(base + UART_O_LCRH) = config;
-
-       /* Clear the flags register */
-       HWREG(base + UART_O_FR) = 0;
-
-       uart_enable(base);
-}
+#if CONFIG_KDEBUG_PORT == KDEBUG_PORT_DBGU
 
-INLINE bool uart_putchar(size_t base, unsigned char ch)
-{
-       if (!(HWREG(base + UART_O_FR) & UART_FR_TXFF))
-       {
-               HWREG(base + UART_O_DR) = ch;
-               return true;
-       }
-       return false;
-}
+#if CONFIG_KDEBUG_PORT == 0
+       #define UART_BASE UART0_BASE
+#elif CONFIG_KDEBUG_PORT == 1
+       #define UART_BASE UART1_BASE
+#elif CONFIG_KDEBUG_PORT == 2
+       #define UART_BASE UART2_BASE
+#else
+       #error "UART port not supported in this board"
+#endif
 
-#if CONFIG_KDEBUG_PORT == KDEBUG_PORT_DBGU
-#define KDBG_WAIT_READY()     while (HWREG(UART0_BASE + UART_O_FR) & UART_FR_BUSY) {}
-#define KDBG_WAIT_TXDONE()    while (!(HWREG(UART0_BASE + UART_O_FR) & UART_FR_TXFE)) {}
+#define KDBG_WAIT_READY()     while (!lm3s_uartReady(UART_BASE)) {}
+#define KDBG_WAIT_TXDONE()    while (!lm3s_uartTxDone(UART_BASE)) {}
 
-#define KDBG_WRITE_CHAR(c)    do { HWREG(UART0_BASE + UART_O_DR) = c; } while(0)
+#define KDBG_WRITE_CHAR(c)    do { lm3s_uartPutCharNonBlocking(UART_BASE, c); } while(0)
 
 /* Debug unit is used only for debug purposes so does not generate interrupts. */
 #define KDBG_MASK_IRQ(old)    do { (void)old; } while(0)
@@ -122,14 +74,6 @@ typedef uint32_t kdbg_irqsave_t;
 
 INLINE void kdbg_hw_init(void)
 {
-       /* Enable the peripheral clock */
-       SYSCTL_RCGC1_R |= SYSCTL_RCGC1_UART0;
-       SYSCTL_RCGC2_R |= SYSCTL_RCGC2_GPIOA;
-       lm3s_busyWait(512);
-
-       /* Set GPIO A0 and A1 as UART pins */
-       lm3s_gpioPinConfig(GPIO_PORTA_BASE, BV(0) | BV(1),
-                       GPIO_DIR_MODE_HW, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD);
-       /* 115.200, 8-bit word, no parity, one stop bit */
-       uart_config(UART0_BASE, CONFIG_KDEBUG_BAUDRATE, UART_LCRH_WLEN_8);
+       /* Initialize UART0 */
+       lm3s_uartInit(CONFIG_KDEBUG_PORT);
 }