#include <string.h> /* memcpy() */
+// Timeout for NAND operations in ms
+#define MT29F_TMOUT 100
// NAND flash status codes
#define MT29F_STATUS_READY BV(6)
#define MT29F_CMD_STATUS 0x70
#define MT29F_CMD_RESET 0xFF
+// Addresses for sending command, addresses and data bytes to flash
+#define MT29F_CMD_ADDR 0x60400000
+#define MT29F_ADDR_ADDR 0x60200000
+#define MT29F_DATA_ADDR 0x60000000
+
struct Mt29fHardware
{
- int boh;
+ uint8_t status;
};
/*
- * Translate flash memory offset in the five address cycles format
- * needed by NAND.
+ * Translate flash page index plus a byte offset
+ * in the five address cycles format needed by NAND.
*
* Cycles in x8 mode as the MT29F2G08AAD
* CA = column addr, PA = page addr, BA = block addr
* Fourth BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8
* Fifth LOW LOW LOW LOW LOW LOW LOW BA16
*/
-static void mt29f_getAddrCycles(size_t offset, uint32_t *cycle0, uint32_t *cycle1234)
+static void mt29f_getAddrCycles(block_idx_t page, size_t offset, uint32_t *cycle0, uint32_t *cycle1234)
{
- /*
- * offset nibbles 77776666 55554444 33332222 11110000
- * cycle1234 -------7 66665555 ----4444 33332222
- * cycle0 11110000
- */
- *cycle0 = offset & 0xFF;
- *cycle1234 = ((offset >> 8) & 0x00000fff) | ((offset >> 4) & 0x01ff0000);
+ ASSERT(offset < MT29F_PAGE_SIZE);
+
+ *cycle0 = offset & 0xff;
+ *cycle1234 = (page << 8) | ((offset >> 8) & 0xf);
+
+ LOG_INFO("mt29f addr: %lx %lx\n", *cycle1234, *cycle0);
}
return SMC_SR & SMC_SR_CMDDONE;
}
-INLINE uint8_t mt29f_isReadyBusy(void)
+static bool mt29f_waitReadyBusy(void)
{
- return SMC_SR & SMC_SR_RB_EDGE0;
+ time_t start = timer_clock();
+
+ while (!(SMC_SR & SMC_SR_RB_EDGE0))
+ {
+ cpu_relax();
+ if (timer_clock() - start > MT29F_TMOUT)
+ {
+ LOG_INFO("mt29f: R/B timeout\n");
+ return false;
+ }
+ }
+
+ return true;
+}
+
+/*
+ * Wait for transfer to complete until timeout.
+ * If transfer completes return true, false in case of timeout.
+ */
+static bool mt29f_waitTransferComplete(void)
+{
+ time_t start = timer_clock();
+
+ while (!(SMC_SR & SMC_SR_XFRDONE))
+ {
+ cpu_relax();
+ if (timer_clock() - start > MT29F_TMOUT)
+ {
+ LOG_INFO("mt29f: xfer complete timeout\n");
+ return false;
+ }
+ }
+
+ return true;
}
/*
* Send command to NAND and wait for completion.
*/
-static void mt29f_sendCommand(uint32_t cmd, uint32_t cycle0, uint32_t cycle1234)
+static void mt29f_sendCommand(uint32_t cmd,
+ int num_cycles, uint32_t cycle0, uint32_t cycle1234)
{
reg32_t *cmd_addr;
while (mt29f_isBusy());
- SMC_ADDR = cycle0;
+ if (num_cycles == 5)
+ SMC_ADDR = cycle0;
cmd_addr = (reg32_t *)(NFC_CMD_BASE_ADDR + cmd);
*cmd_addr = cycle1234;
mt29f_sendCommand(
NFC_CMD_NFCCMD | MT29F_CSID | NFC_CMD_ACYCLE_NONE |
- MT29F_CMD_STATUS << 2, 0, 0);
+ MT29F_CMD_STATUS << 2,
+ 0, 0, 0);
status = (uint8_t)HWREG(MT29F_DATA_ADDR);
return (status & MT29F_STATUS_READY) && !(status & MT29F_STATUS_ERROR);
}
-#if 0 //reset
+static void mt29f_reset(void)
+{
mt29f_sendCommand(
- NFC_CMD_NFCCMD | MT29F_CSID | NFC_CMD_ACYCLE_NONE |
- MT29F_CMD_RESET << 2,
- 0, /* Dummy address cylce 1,2,3,4.*/
- 0 /* Dummy address cylce 0.*/
-#endif
+ NFC_CMD_NFCCMD | MT29F_CSID | NFC_CMD_ACYCLE_NONE |
+ MT29F_CMD_RESET << 2,
+ 0, 0, 0);
+
+ mt29f_waitReadyBusy();
+}
+
/**
- * Erase block at given offset.
+ * Erase the whole block containing given page.
*/
-int mt29f_blockErase(Mt29f *fls, size_t blk_offset)
+int mt29f_blockErase(Mt29f *fls, block_idx_t page)
{
uint32_t cycle0;
uint32_t cycle1234;
- mt29f_getAddrCycles(blk_offset, &cycle0, &cycle1234);
+ mt29f_getAddrCycles(page, 0, &cycle0, &cycle1234);
mt29f_sendCommand(
NFC_CMD_NFCCMD | MT29F_CSID | NFC_CMD_ACYCLE_THREE | NFC_CMD_VCMD2 |
(MT29F_CMD_ERASE_2 << 10) | (MT29F_CMD_ERASE_1 << 2),
- cycle1234, 0);
+ 3, 0, cycle1234 >> 8);
- while (!mt29f_isReadyBusy());
+ mt29f_waitReadyBusy();
if (!mt29f_isOperationComplete())
{
LOG_ERR("mt29f: error erasing block\n");
+ fls->hw->status |= MT29F_ERR_ERASE;
return -1;
}
}
+/**
+ * Read Device ID and configuration codes.
+ */
+bool mt29f_getDevId(Mt29f *fls, uint8_t dev_id[5])
+{
+ mt29f_sendCommand(
+ NFC_CMD_NFCCMD | NFC_CMD_NFCEN | MT29F_CSID | NFC_CMD_ACYCLE_ONE |
+ MT29F_CMD_READID << 2,
+ 1, 0, 0);
+
+ mt29f_waitReadyBusy();
+ if (!mt29f_waitTransferComplete())
+ {
+ LOG_ERR("mt29f: getDevId timeout\n");
+ fls->hw->status |= MT29F_ERR_RD_TMOUT;
+ return false;
+ }
+
+ memcpy(dev_id, (void *)NFC_SRAM_BASE_ADDR, 5);
+ return true;
+}
+
+
static size_t mt29f_readDirect(struct KBlock *blk, block_idx_t idx, void *buf, size_t offset, size_t size)
{
+ Mt29f *fls = FLASH_CAST(blk);
+ uint32_t cycle0;
+ uint32_t cycle1234;
+
+ ASSERT(offset == 0);
+ ASSERT(size == blk->blk_size);
+
+ LOG_INFO("mt29f_readDirect\n");
+
+ mt29f_getAddrCycles(idx, 0, &cycle0, &cycle1234);
+
+ mt29f_sendCommand(
+ NFC_CMD_NFCCMD | NFC_CMD_NFCEN | MT29F_CSID | NFC_CMD_ACYCLE_FIVE | NFC_CMD_VCMD2 |
+ (MT29F_CMD_READ_2 << 10) | (MT29F_CMD_READ_1 << 2),
+ 5, cycle0, cycle1234);
+
+ mt29f_waitReadyBusy();
+ if (!mt29f_waitTransferComplete())
+ {
+ LOG_ERR("mt29f: read timeout\n");
+ fls->hw->status |= MT29F_ERR_RD_TMOUT;
+ return 0;
+ }
+
+ if (!kblock_buffered(blk) && (buf != (void *)NFC_SRAM_BASE_ADDR))
+ memcpy(buf, (void *)NFC_SRAM_BASE_ADDR, size);
+
+ return size;
}
static size_t mt29f_writeDirect(struct KBlock *blk, block_idx_t idx, const void *_buf, size_t offset, size_t size)
{
+ Mt29f *fls = FLASH_CAST(blk);
+ uint32_t cycle0;
+ uint32_t cycle1234;
+
+ ASSERT(offset == 0);
+ ASSERT(size == blk->blk_size);
+
+ LOG_INFO("mt29f_writeDirect\n");
+
+ if (!kblock_buffered(blk) && (_buf != (void *)NFC_SRAM_BASE_ADDR))
+ memcpy((void *)NFC_SRAM_BASE_ADDR, _buf, size);
+
+ mt29f_getAddrCycles(idx, 0, &cycle0, &cycle1234);
+
+ mt29f_sendCommand(
+ NFC_CMD_NFCCMD | NFC_CMD_NFCWR | NFC_CMD_NFCEN | MT29F_CSID | NFC_CMD_ACYCLE_FIVE |
+ MT29F_CMD_WRITE_1 << 2,
+ 5, cycle0, cycle1234);
+
+ if (!mt29f_waitTransferComplete())
+ {
+ LOG_ERR("mt29f: write timeout\n");
+ fls->hw->status |= MT29F_ERR_WR_TMOUT;
+ return 0;
+ }
+
+ mt29f_sendCommand(
+ NFC_CMD_NFCCMD | MT29F_CSID | NFC_CMD_ACYCLE_NONE |
+ MT29F_CMD_WRITE_2 << 2,
+ 0, 0, 0);
+
+ mt29f_waitReadyBusy();
+
+ if (!mt29f_isOperationComplete())
+ {
+ LOG_ERR("mt29f: error writing page\n");
+ fls->hw->status |= MT29F_ERR_WRITE;
+ return 0;
+ }
+
+ return size;
}
static int mt29f_error(struct KBlock *blk)
{
Mt29f *fls = FLASH_CAST(blk);
+ return fls->hw->status;
}
static void mt29f_clearerror(struct KBlock *blk)
{
Mt29f *fls = FLASH_CAST(blk);
+ fls->hw->status = 0;
}
SMC_MODE0 = SMC_MODE_READ_MODE
| SMC_MODE_WRITE_MODE;
+
+ SMC_CFG = SMC_CFG_PAGESIZE_PS2048_64
+ | SMC_CFG_EDGECTRL
+ | SMC_CFG_DTOMUL_X1048576
+ | SMC_CFG_DTOCYC(0xF);
+
+ // Disable SMC interrupts, reset and enable NFC controller
+ SMC_IDR = ~0;
+ SMC_CTRL = 0;
+ SMC_CTRL = SMC_CTRL_NFCEN;
+
+ mt29f_reset();
}
-void mt29f_hw_init(Mt29f *fls)
+void mt29f_init(Mt29f *fls)
{
common_init(fls);
fls->blk.priv.vt = &mt29f_buffered_vt;
- fls->blk.priv.flags |= KB_BUFFERED | KB_PARTIAL_WRITE;
- fls->blk.priv.buf = (void *)NFC_CMD_BASE_ADDR;
+ fls->blk.priv.flags |= KB_BUFFERED;
+ fls->blk.priv.buf = (void *)NFC_SRAM_BASE_ADDR;
// Load the first block in the cache
- void *start = 0x0;
- memcpy(fls->blk.priv.buf, start, fls->blk.blk_size);
+ mt29f_readDirect(&fls->blk, 0, (void *)NFC_SRAM_BASE_ADDR, 0, MT29F_PAGE_SIZE);
}
-void mt29f_hw_initUnbuffered(Mt29f *fls)
+void mt29f_initUnbuffered(Mt29f *fls)
{
common_init(fls);
fls->blk.priv.vt = &mt29f_unbuffered_vt;
projects / bertos.git / blobdiff