Remove duplicate define. Put all phy chip specific defines in its

[bertos.git] / bertos / cpu / cortex-m3 / drv / nand_sam3.c

diff --git a/bertos/cpu/cortex-m3/drv/nand_sam3.c b/bertos/cpu/cortex-m3/drv/nand_sam3.c
index b71d5e7649013432b0b39bd5a6f5550ae9a17ca8..85350cb761a58a5aa65804b39221b5f27e445a78 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/nand_sam3.c
+++ b/bertos/cpu/cortex-m3/drv/nand_sam3.c
@@ -30,21 +30,16 @@
  *
  * -->
  *
- * \brief NAND driver for SAM3's static memory controller.
+ * \brief NAND driver hardware implementation for SAM3's static memory controller.
  *
  * \author Stefano Fedrigo <aleph@develer.com>
  */
 
-#include "nand_sam3.h"
 #include <drv/nand.h>
 #include <cfg/log.h>
-#include <cfg/macros.h>
 #include <io/sam3.h>
 #include <drv/timer.h>
-#include <cpu/power.h> /* cpu_relax() */
-#include <cpu/types.h>
-
-#include <string.h> /* memcpy, memset */
+#include <cpu/power.h> // cpu_relax()
 
 
 /*
@@ -72,7 +67,7 @@
  * signal.
  * Return true for edge detection, false in case of timeout.
  */
-bool nand_waitReadyBusy(UNUSED_ARG(Mt29f *, chip), time_t timeout)
+bool nand_waitReadyBusy(UNUSED_ARG(Nand *, chip), time_t timeout)
 {
        time_t start = timer_clock();
 
@@ -89,11 +84,12 @@ bool nand_waitReadyBusy(UNUSED_ARG(Mt29f *, chip), time_t timeout)
        return true;
 }
 
+
 /*
  * Wait for transfer to complete until timeout.
  * If transfer completes return true, false in case of timeout.
  */
-bool nand_waitTransferComplete(UNUSED_ARG(Mt29f *, chip), time_t timeout)
+bool nand_waitTransferComplete(UNUSED_ARG(Nand *, chip), time_t timeout)
 {
        time_t start = timer_clock();
 
@@ -114,7 +110,7 @@ bool nand_waitTransferComplete(UNUSED_ARG(Mt29f *, chip), time_t timeout)
 /*
  * Send command to NAND and wait for completion.
  */
-void nand_sendCommand(Mt29f *chip,
+void nand_sendCommand(Nand *chip,
                uint32_t cmd1, uint32_t cmd2,
                int num_cycles, uint32_t cycle0, uint32_t cycle1234)
 {
@@ -157,25 +153,31 @@ void nand_sendCommand(Mt29f *chip,
  * NOTE: this is global between different chip selects, so returns
  * the status register of the last used NAND chip.
  */
-uint8_t nand_getChipStatus(UNUSED_ARG(Mt29f *, chip))
+uint8_t nand_getChipStatus(UNUSED_ARG(Nand *, chip))
 {
        return (uint8_t)HWREG(NFC_CMD_BASE_ADDR);
 }
 
 
-void *nand_dataBuffer(UNUSED_ARG(Mt29f *, chip))
+/*
+ * Return pointer to buffer where data are read to or written from
+ * by nand_sendCommand().
+ */
+void *nand_dataBuffer(UNUSED_ARG(Nand *, chip))
 {
        return (void *)NFC_SRAM_BASE_ADDR;
 }
 
 
-bool nand_checkEcc(Mt29f *chip)
+/*
+ * Extract ECC data from ECC_PRx registers.
+ */
+bool nand_checkEcc(UNUSED_ARG(Nand *, chip))
 {
        uint32_t sr1 = SMC_ECC_SR1;
        if (sr1)
        {
                LOG_INFO("ECC error, ECC_SR1=0x%lx\n", sr1);
-               chip->status |= NAND_ERR_ECC;
                return false;
        }
        else
@@ -192,7 +194,7 @@ bool nand_checkEcc(Mt29f *chip)
  * \param ecc       pointer to buffer where computed ECC is stored
  * \param ecc_size  max size for ecc buffer
  */
-void nand_computeEcc(UNUSED_ARG(Mt29f *, chip),
+void nand_computeEcc(UNUSED_ARG(Nand *, chip),
                UNUSED_ARG(const void *, buf), UNUSED_ARG(size_t, size), uint32_t *ecc, size_t ecc_size)
 {
        size_t i;
@@ -201,7 +203,10 @@ void nand_computeEcc(UNUSED_ARG(Mt29f *, chip),
 }
 
 
-void nand_hwInit(UNUSED_ARG(Mt29f *, chip))
+/*
+ * Low-level hardware driver initialization.
+ */
+void nand_hwInit(UNUSED_ARG(Nand *, chip))
 {
        // FIXME: Parameters specific for MT29F8G08AAD