We use same gpio port reg.

[bertos.git] / bertos / cpu / cortex-m3 / drv / ser_stm32.c

diff --git a/bertos/cpu/cortex-m3/drv/ser_stm32.c b/bertos/cpu/cortex-m3/drv/ser_stm32.c
index 315329bd8adae1391dd438ea4c98b737afefe039..081a057997ac90e589e145235a630cf282d98b47 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/ser_stm32.c
+++ b/bertos/cpu/cortex-m3/drv/ser_stm32.c
@@ -145,21 +145,19 @@ void stm32_uartInit(int port)
 {
        struct stm32_usart *base = (struct stm32_usart *)UARTDesc[port].base;
 
-       kprintf("init port[%d]cnt[%d]\n", port, SER_CNT);
        ASSERT(port >= 0 && port < SER_CNT);
 
        /* Enable clocking on AFIO */
        RCC->APB2ENR |= RCC_APB2_AFIO;
+       RCC->APB2ENR |=  gpio_uart[port].sysctl;
 
        /* Configure USART pins */
        if (port == USART1_PORT)
        {
-               RCC->APB2ENR |=  gpio_uart[port].sysctl;
                RCC->APB2ENR |=  gpio_uart[port].sysctl1;
        }
        else
        {
-               RCC->APB1ENR |=  gpio_uart[port].sysctl;
                RCC->APB1ENR |=  gpio_uart[port].sysctl1;
        }
 
@@ -183,9 +181,6 @@ void stm32_uartInit(int port)
        /* Enable trasmision and receiver */
        base->CR1 |= (BV(CR1_TE) | BV(CR1_RE));
 
-
-       kprintf("INIT[%02x]\n", (uint8_t)base->SR); \
-
 }
 
 static bool tx_sending(struct SerialHardware *_hw)
@@ -221,7 +216,7 @@ static void uart_irq_tx(int port)
                 * Disable TX empty interrupts if there're no more
                 * characters to transmit.
                 */
-               base->CR1 &= ~BV(7);
+               base->CR1 &= ~BV(CR1_TXEIE);
                UARTDesc[port].sending = false;
        }
        else
@@ -237,12 +232,17 @@ static void uart_common_irq_handler(int port)
 
        /* Read and clear the IRQ status */
        status = base->SR;
+
+       /* Check hw errors */
+       ser_handles[port]->status = status &
+               (BV(SR_ORE) | BV(SR_FE) | BV(SR_PE) | BV(SR_NE));
+
        /* Process the IRQ */
-       if (status & BV(5))
+       if (status & BV(CR1_RXNEIE))
        {
                uart_irq_rx(port);
        }
-       if (status & (BV(7) | BV(6)))
+       if (status & (BV(CR1_TXEIE) | BV(CR1_TCIE)))
        {
                uart_irq_tx(port);
        }
@@ -255,14 +255,14 @@ static void stm32_uartIRQEnable(int port, sysirq_handler_t handler)
        /* Register the IRQ handler */
        sysirq_setHandler(UARTDesc[port].irq, handler);
 
-       base->CR1 |= BV(5);
+       base->CR1 |= BV(CR1_RXNEIE);
 }
 
 static void stm32_uartIRQDisable(int port)
 {
        struct stm32_usart *base = (struct stm32_usart *)UARTDesc[port].base;
 
-       base->CR1 &= ~(BV(5) | USART_FLAG_TXE);
+       base->CR1 &= ~(BV(CR1_RXNEIE) | USART_FLAG_TXE);
 }
 
 
@@ -289,9 +289,8 @@ static void stm32_uartIRQDisable(int port)
                stm32_uartPutChar(USART ## port ## _BASE, fifo_pop(txfifo));    \
                if (!fifo_isempty(txfifo))                                      \
                {                                                               \
-                       kputs("tx_en_irq\n"); \
                        hw->sending = true;      \
-                       base->CR1 |= BV(7); \
+                       base->CR1 |= BV(CR1_TXEIE); \
                } \
        }                                                                       \
                                                                                \