We use same gpio port reg.

[bertos.git] / bertos / cpu / cortex-m3 / drv / ser_stm32.c

diff --git a/bertos/cpu/cortex-m3/drv/ser_stm32.c b/bertos/cpu/cortex-m3/drv/ser_stm32.c
index 6fdcf312feda3f98e354f894b38a69471e313e40..081a057997ac90e589e145235a630cf282d98b47 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/ser_stm32.c
+++ b/bertos/cpu/cortex-m3/drv/ser_stm32.c
@@ -149,16 +149,15 @@ void stm32_uartInit(int port)
 
        /* Enable clocking on AFIO */
        RCC->APB2ENR |= RCC_APB2_AFIO;
+       RCC->APB2ENR |=  gpio_uart[port].sysctl;
 
        /* Configure USART pins */
        if (port == USART1_PORT)
        {
-               RCC->APB2ENR |=  gpio_uart[port].sysctl;
                RCC->APB2ENR |=  gpio_uart[port].sysctl1;
        }
        else
        {
-               RCC->APB1ENR |=  gpio_uart[port].sysctl;
                RCC->APB1ENR |=  gpio_uart[port].sysctl1;
        }
 
@@ -233,6 +232,11 @@ static void uart_common_irq_handler(int port)
 
        /* Read and clear the IRQ status */
        status = base->SR;
+
+       /* Check hw errors */
+       ser_handles[port]->status = status &
+               (BV(SR_ORE) | BV(SR_FE) | BV(SR_PE) | BV(SR_NE));
+
        /* Process the IRQ */
        if (status & BV(CR1_RXNEIE))
        {