uint32_t rx_pin;
uint32_t tx_pin;
/* Sysctl */
- uint32_t sysctl;
- uint32_t sysctl1;
+ uint32_t sysctl_gpio;
+ uint32_t sysctl_usart;
};
.base = GPIOA_BASE,
.rx_pin = GPIO_USART1_RX_PIN,
.tx_pin = GPIO_USART1_TX_PIN,
- .sysctl = RCC_APB2_GPIOA,
- .sysctl1 = RCC_APB2_USART1,
+ .sysctl_gpio = RCC_APB2_GPIOA,
+ .sysctl_usart = RCC_APB2_USART1,
},
/* UART2 */
{
.base = GPIOA_BASE,
.rx_pin = GPIO_USART2_RX_PIN,
.tx_pin = GPIO_USART2_TX_PIN,
- .sysctl = RCC_APB2_GPIOA,
- .sysctl1 = RCC_APB1_USART2,
+ .sysctl_gpio = RCC_APB2_GPIOA,
+ .sysctl_usart = RCC_APB1_USART2,
},
/* UART3 */
{
.base = GPIOB_BASE,
.rx_pin = GPIO_USART3_RX_PIN,
.tx_pin = GPIO_USART3_TX_PIN,
- .sysctl = RCC_APB2_GPIOB,
- .sysctl1 = RCC_APB1_USART3,
+ .sysctl_gpio = RCC_APB2_GPIOB,
+ .sysctl_usart = RCC_APB1_USART3,
},
};
{
struct stm32_usart *base = (struct stm32_usart *)UARTDesc[port].base;
- kprintf("init port[%d]cnt[%d]\n", port, SER_CNT);
ASSERT(port >= 0 && port < SER_CNT);
/* Enable clocking on AFIO */
RCC->APB2ENR |= RCC_APB2_AFIO;
+ RCC->APB2ENR |= gpio_uart[port].sysctl_gpio;
/* Configure USART pins */
if (port == USART1_PORT)
{
- RCC->APB2ENR |= gpio_uart[port].sysctl;
- RCC->APB2ENR |= gpio_uart[port].sysctl1;
+ RCC->APB2ENR |= gpio_uart[port].sysctl_usart;
}
else
{
- RCC->APB1ENR |= gpio_uart[port].sysctl;
- RCC->APB1ENR |= gpio_uart[port].sysctl1;
+ RCC->APB1ENR |= gpio_uart[port].sysctl_usart;
}
stm32_gpioPinConfig((struct stm32_gpio *)gpio_uart[port].base, gpio_uart[port].tx_pin,
GPIO_MODE_IN_FLOATING, GPIO_SPEED_50MHZ);
/* Clear control registry */
- base->CR2 = 0; //CR2_CLEAR_MASK;
- base->CR1 = 0; //CR1_CLEAR_MASK;
- base->CR3 = 0; //CR3_CLEAR_MASK;
+ base->CR2 = 0;
+ base->CR1 = 0;
+ base->CR3 = 0;
base->SR = 0;
/* Set serial param: 115.200 bps, no parity */
/* Enable trasmision and receiver */
base->CR1 |= (BV(CR1_TE) | BV(CR1_RE));
-
- kprintf("INIT[%02x]\n", (uint8_t)base->SR); \
-
}
static bool tx_sending(struct SerialHardware *_hw)
* Disable TX empty interrupts if there're no more
* characters to transmit.
*/
- base->CR1 &= ~BV(7);
+ base->CR1 &= ~BV(CR1_TXEIE);
UARTDesc[port].sending = false;
}
else
/* Read and clear the IRQ status */
status = base->SR;
+
+ /* Check hw errors */
+ ser_handles[port]->status = status &
+ (BV(SR_ORE) | BV(SR_FE) | BV(SR_PE) | BV(SR_NE));
+
/* Process the IRQ */
- if (status & BV(5))
+ if (status & BV(CR1_RXNEIE))
{
uart_irq_rx(port);
}
- if (status & (BV(7) | BV(6)))
+ if (status & (BV(CR1_TXEIE) | BV(CR1_TCIE)))
{
uart_irq_tx(port);
}
/* Register the IRQ handler */
sysirq_setHandler(UARTDesc[port].irq, handler);
- base->CR1 |= BV(5);
+ base->CR1 |= BV(CR1_RXNEIE);
}
static void stm32_uartIRQDisable(int port)
{
struct stm32_usart *base = (struct stm32_usart *)UARTDesc[port].base;
- base->CR1 &= ~(BV(5) | USART_FLAG_TXE);
+ base->CR1 &= ~(BV(CR1_RXNEIE) | USART_FLAG_TXE);
}
stm32_uartPutChar(USART ## port ## _BASE, fifo_pop(txfifo)); \
if (!fifo_isempty(txfifo)) \
{ \
- kputs("tx_en_irq\n"); \
hw->sending = true; \
- base->CR1 |= BV(7); \
+ base->CR1 |= BV(CR1_TXEIE); \
} \
} \
\