Add some missign register defines. Reformat.

[bertos.git] / bertos / cpu / cortex-m3 / drv / timer_cm3.c

diff --git a/bertos/cpu/cortex-m3/drv/timer_cm3.c b/bertos/cpu/cortex-m3/drv/timer_cm3.c
index a4d9668943d35bf186c80d30ce5fcd948efdfe85..ac8512e469a0c914896cea4fcb62f5ac72235e06 100644 (file)
--- a/bertos/cpu/cortex-m3/drv/timer_cm3.c
+++ b/bertos/cpu/cortex-m3/drv/timer_cm3.c
@@ -35,26 +35,29 @@
  * \author Andrea Righi <arighi@develer.com>
  */
 
+#include "timer_cm3.h"
+
 #include <cfg/debug.h>
+
 #include <cpu/irq.h>
+
 #include <drv/irq_cm3.h>
-#include "timer_cm3.h"
 
 INLINE void timer_hw_setPeriod(unsigned long period)
 {
        ASSERT(period < (1 << 24));
-       HWREG(NVIC_ST_RELOAD) = period - 1;
+       NVIC_ST_RELOAD_R = period - 1;
 }
 
 static void timer_hw_enable(void)
 {
-       HWREG(NVIC_ST_CTRL) |=
+       NVIC_ST_CTRL_R |=
                NVIC_ST_CTRL_CLK_SRC | NVIC_ST_CTRL_ENABLE | NVIC_ST_CTRL_INTEN;
 }
 
 static void timer_hw_disable(void)
 {
-       HWREG(NVIC_ST_CTRL) &= ~(NVIC_ST_CTRL_ENABLE | NVIC_ST_CTRL_INTEN);
+       NVIC_ST_CTRL_R &= ~(NVIC_ST_CTRL_ENABLE | NVIC_ST_CTRL_INTEN);
 }
 
 void timer_hw_init(void)