#define FLASH_ERASE_SIZE 0x00000400
/*\}*/
-/**
- * The following are defines for the bit fields in the SYSCTL_DID0 register.
- */
-/*\{*/
-#define SYSCTL_DID0_VER_M 0x70000000 ///< DID0 Version
-#define SYSCTL_DID0_VER_1 0x10000000 ///< Second version of the DID0
- ///< register format
-#define SYSCTL_DID0_CLASS_M 0x00FF0000 ///< Device Class
-#define SYSCTL_DID0_CLASS_FURY 0x00010000 ///< Stellaris(R) Fury-class devices
-#define SYSCTL_DID0_MAJ_M 0x0000FF00 ///< Major Revision
-#define SYSCTL_DID0_MAJ_REVA 0x00000000 ///< Revision A (initial device)
-#define SYSCTL_DID0_MAJ_REVB 0x00000100 ///< Revision B (first base layer
- ///< revision)
-#define SYSCTL_DID0_MAJ_REVC 0x00000200 ///< Revision C (second base layer
- ///< revision)
-#define SYSCTL_DID0_MIN_M 0x000000FF ///< Minor Revision
-#define SYSCTL_DID0_MIN_0 0x00000000 ///< Initial device, or a major
- ///< revision update
-#define SYSCTL_DID0_MIN_1 0x00000001 ///< First metal layer change
-#define SYSCTL_DID0_MIN_2 0x00000002 ///< Second metal layer change
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the SYSCTL_DID1 register.
- */
-/*\{*/
-#define SYSCTL_DID1_VER_M 0xF0000000 ///< DID1 Version
-#define SYSCTL_DID1_VER_1 0x10000000 ///< Second version of the DID1
- ///< register format
-#define SYSCTL_DID1_FAM_M 0x0F000000 ///< Family
-#define SYSCTL_DID1_FAM_STELLARIS \
- 0x00000000 ///< Stellaris family of
- ///< microcontollers, that is, all
- ///< devices with external part
- ///< numbers starting with LM3S
-#define SYSCTL_DID1_PRTNO_M 0x00FF0000 ///< Part Number
-#define SYSCTL_DID1_PRTNO_1968 0x00B80000 ///< LM3S1968
-#define SYSCTL_DID1_PINCNT_M 0x0000E000 ///< Package Pin Count
-#define SYSCTL_DID1_PINCNT_100 0x00004000 ///< 100-pin package
-#define SYSCTL_DID1_TEMP_M 0x000000E0 ///< Temperature Range
-#define SYSCTL_DID1_TEMP_C 0x00000000 ///< Commercial temperature range (0C
- ///< to 70C)
-#define SYSCTL_DID1_TEMP_I 0x00000020 ///< Industrial temperature range
- ///< (-40C to 85C)
-#define SYSCTL_DID1_TEMP_E 0x00000040 ///< Extended temperature range (-40C
- ///< to 105C)
-#define SYSCTL_DID1_PKG_M 0x00000018 ///< Package Type
-#define SYSCTL_DID1_PKG_SOIC 0x00000000 ///< SOIC package
-#define SYSCTL_DID1_PKG_QFP 0x00000008 ///< LQFP package
-#define SYSCTL_DID1_PKG_BGA 0x00000010 ///< BGA package
-#define SYSCTL_DID1_ROHS 0x00000004 ///< RoHS-Compliance
-#define SYSCTL_DID1_QUAL_M 0x00000003 ///< Qualification Status
-#define SYSCTL_DID1_QUAL_ES 0x00000000 ///< Engineering Sample (unqualified)
-#define SYSCTL_DID1_QUAL_PP 0x00000001 ///< Pilot Production (unqualified)
-#define SYSCTL_DID1_QUAL_FQ 0x00000002 ///< Fully Qualified
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the SYSCTL_DC0 register.
- */
-/*\{*/
-#define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 ///< SRAM Size
-#define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 ///< 64 KB of SRAM
-#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF ///< Flash Size
-#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F ///< 256 KB of Flash
-#define SYSCTL_DC0_SRAMSZ_S 16 ///< SRAM size shift
-#define SYSCTL_DC0_FLASHSZ_S 0 ///< Flash size shift
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the SYSCTL_DC1 register.
- */
-/*\{*/
-#define SYSCTL_DC1_PWM 0x00100000 ///< PWM Module Present
-#define SYSCTL_DC1_ADC 0x00010000 ///< ADC Module Present
-#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 ///< System Clock Divider
-#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 ///< Specifies a 50-MHz CPU clock
- ///< with a PLL divider of 4
-#define SYSCTL_DC1_ADCSPD_M 0x00000300 ///< Max ADC Speed
-#define SYSCTL_DC1_ADCSPD_1M 0x00000300 ///< 1M samples/second
-#define SYSCTL_DC1_MPU 0x00000080 ///< MPU Present
-#define SYSCTL_DC1_HIB 0x00000040 ///< Hibernation Module Present
-#define SYSCTL_DC1_TEMP 0x00000020 ///< Temp Sensor Present
-#define SYSCTL_DC1_PLL 0x00000010 ///< PLL Present
-#define SYSCTL_DC1_WDT 0x00000008 ///< Watchdog Timer Present
-#define SYSCTL_DC1_SWO 0x00000004 ///< SWO Trace Port Present
-#define SYSCTL_DC1_SWD 0x00000002 ///< SWD Present
-#define SYSCTL_DC1_JTAG 0x00000001 ///< JTAG Present
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the SYSCTL_DC2 register.
- */
-/*\{*/
-#define SYSCTL_DC2_COMP2 0x04000000 ///< Analog Comparator 2 Present
-#define SYSCTL_DC2_COMP1 0x02000000 ///< Analog Comparator 1 Present
-#define SYSCTL_DC2_COMP0 0x01000000 ///< Analog Comparator 0 Present
-#define SYSCTL_DC2_TIMER3 0x00080000 ///< Timer Module 3 Present
-#define SYSCTL_DC2_TIMER2 0x00040000 ///< Timer Module 2 Present
-#define SYSCTL_DC2_TIMER1 0x00020000 ///< Timer Module 1 Present
-#define SYSCTL_DC2_TIMER0 0x00010000 ///< Timer Module 0 Present
-#define SYSCTL_DC2_I2C1 0x00004000 ///< I2C Module 1 Present
-#define SYSCTL_DC2_I2C0 0x00001000 ///< I2C Module 0 Present
-#define SYSCTL_DC2_QEI1 0x00000200 ///< QEI Module 1 Present
-#define SYSCTL_DC2_QEI0 0x00000100 ///< QEI Module 0 Present
-#define SYSCTL_DC2_SSI1 0x00000020 ///< SSI Module 1 Present
-#define SYSCTL_DC2_SSI0 0x00000010 ///< SSI Module 0 Present
-#define SYSCTL_DC2_UART2 0x00000004 ///< UART Module 2 Present
-#define SYSCTL_DC2_UART1 0x00000002 ///< UART Module 1 Present
-#define SYSCTL_DC2_UART0 0x00000001 ///< UART Module 0 Present
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the SYSCTL_DC3 register.
- */
-/*\{*/
-#define SYSCTL_DC3_32KHZ 0x80000000 ///< 32KHz Input Clock Available
-#define SYSCTL_DC3_CCP3 0x08000000 ///< CCP3 Pin Present
-#define SYSCTL_DC3_CCP2 0x04000000 ///< CCP2 Pin Present
-#define SYSCTL_DC3_CCP1 0x02000000 ///< CCP1 Pin Present
-#define SYSCTL_DC3_CCP0 0x01000000 ///< CCP0 Pin Present
-#define SYSCTL_DC3_ADC7 0x00800000 ///< ADC7 Pin Present
-#define SYSCTL_DC3_ADC6 0x00400000 ///< ADC6 Pin Present
-#define SYSCTL_DC3_ADC5 0x00200000 ///< ADC5 Pin Present
-#define SYSCTL_DC3_ADC4 0x00100000 ///< ADC4 Pin Present
-#define SYSCTL_DC3_ADC3 0x00080000 ///< ADC3 Pin Present
-#define SYSCTL_DC3_ADC2 0x00040000 ///< ADC2 Pin Present
-#define SYSCTL_DC3_ADC1 0x00020000 ///< ADC1 Pin Present
-#define SYSCTL_DC3_ADC0 0x00010000 ///< ADC0 Pin Present
-#define SYSCTL_DC3_PWMFAULT 0x00008000 ///< PWM Fault Pin Present
-#define SYSCTL_DC3_C2PLUS 0x00002000 ///< C2+ Pin Present
-#define SYSCTL_DC3_C2MINUS 0x00001000 ///< C2- Pin Present
-#define SYSCTL_DC3_C1PLUS 0x00000400 ///< C1+ Pin Present
-#define SYSCTL_DC3_C1MINUS 0x00000200 ///< C1- Pin Present
-#define SYSCTL_DC3_C0O 0x00000100 ///< C0o Pin Present
-#define SYSCTL_DC3_C0PLUS 0x00000080 ///< C0+ Pin Present
-#define SYSCTL_DC3_C0MINUS 0x00000040 ///< C0- Pin Present
-#define SYSCTL_DC3_PWM5 0x00000020 ///< PWM5 Pin Present
-#define SYSCTL_DC3_PWM4 0x00000010 ///< PWM4 Pin Present
-#define SYSCTL_DC3_PWM3 0x00000008 ///< PWM3 Pin Present
-#define SYSCTL_DC3_PWM2 0x00000004 ///< PWM2 Pin Present
-#define SYSCTL_DC3_PWM1 0x00000002 ///< PWM1 Pin Present
-#define SYSCTL_DC3_PWM0 0x00000001 ///< PWM0 Pin Present
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the SYSCTL_DC4 register.
- */
-/*\{*/
-#define SYSCTL_DC4_GPIOH 0x00000080 ///< GPIO Port H Present
-#define SYSCTL_DC4_GPIOG 0x00000040 ///< GPIO Port G Present
-#define SYSCTL_DC4_GPIOF 0x00000020 ///< GPIO Port F Present
-#define SYSCTL_DC4_GPIOE 0x00000010 ///< GPIO Port E Present
-#define SYSCTL_DC4_GPIOD 0x00000008 ///< GPIO Port D Present
-#define SYSCTL_DC4_GPIOC 0x00000004 ///< GPIO Port C Present
-#define SYSCTL_DC4_GPIOB 0x00000002 ///< GPIO Port B Present
-#define SYSCTL_DC4_GPIOA 0x00000001 ///< GPIO Port A Present
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the SYSCTL_PBORCTL register.
- */
-/*\{*/
-#define SYSCTL_PBORCTL_BORIOR 0x00000002 ///< BOR Interrupt or Reset
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the SYSCTL_LDOPCTL register.
- */
-/*\{*/
-#define SYSCTL_LDOPCTL_M 0x0000003F ///< LDO Output Voltage
-#define SYSCTL_LDOPCTL_2_50V 0x00000000 ///< 2.50
-#define SYSCTL_LDOPCTL_2_45V 0x00000001 ///< 2.45
-#define SYSCTL_LDOPCTL_2_40V 0x00000002 ///< 2.40
-#define SYSCTL_LDOPCTL_2_35V 0x00000003 ///< 2.35
-#define SYSCTL_LDOPCTL_2_30V 0x00000004 ///< 2.30
-#define SYSCTL_LDOPCTL_2_25V 0x00000005 ///< 2.25
-#define SYSCTL_LDOPCTL_2_75V 0x0000001B ///< 2.75
-#define SYSCTL_LDOPCTL_2_70V 0x0000001C ///< 2.70
-#define SYSCTL_LDOPCTL_2_65V 0x0000001D ///< 2.65
-#define SYSCTL_LDOPCTL_2_60V 0x0000001E ///< 2.60
-#define SYSCTL_LDOPCTL_2_55V 0x0000001F ///< 2.55
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the SYSCTL_SRCR0 register.
- */
-/*\{*/
-#define SYSCTL_SRCR0_PWM 0x00100000 ///< PWM Reset Control
-#define SYSCTL_SRCR0_ADC 0x00010000 ///< ADC0 Reset Control
-#define SYSCTL_SRCR0_HIB 0x00000040 ///< HIB Reset Control
-#define SYSCTL_SRCR0_WDT 0x00000008 ///< WDT Reset Control
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the SYSCTL_SRCR1 register.
- */
-/*\{*/
-#define SYSCTL_SRCR1_COMP2 0x04000000 ///< Analog Comp 2 Reset Control
-#define SYSCTL_SRCR1_COMP1 0x02000000 ///< Analog Comp 1 Reset Control
-#define SYSCTL_SRCR1_COMP0 0x01000000 ///< Analog Comp 0 Reset Control
-#define SYSCTL_SRCR1_TIMER3 0x00080000 ///< Timer 3 Reset Control
-#define SYSCTL_SRCR1_TIMER2 0x00040000 ///< Timer 2 Reset Control
-#define SYSCTL_SRCR1_TIMER1 0x00020000 ///< Timer 1 Reset Control
-#define SYSCTL_SRCR1_TIMER0 0x00010000 ///< Timer 0 Reset Control
-#define SYSCTL_SRCR1_I2C1 0x00004000 ///< I2C1 Reset Control
-#define SYSCTL_SRCR1_I2C0 0x00001000 ///< I2C0 Reset Control
-#define SYSCTL_SRCR1_QEI1 0x00000200 ///< QEI1 Reset Control
-#define SYSCTL_SRCR1_QEI0 0x00000100 ///< QEI0 Reset Control
-#define SYSCTL_SRCR1_SSI1 0x00000020 ///< SSI1 Reset Control
-#define SYSCTL_SRCR1_SSI0 0x00000010 ///< SSI0 Reset Control
-#define SYSCTL_SRCR1_UART2 0x00000004 ///< UART2 Reset Control
-#define SYSCTL_SRCR1_UART1 0x00000002 ///< UART1 Reset Control
-#define SYSCTL_SRCR1_UART0 0x00000001 ///< UART0 Reset Control
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the SYSCTL_SRCR2 register.
- */
-/*\{*/
-#define SYSCTL_SRCR2_GPIOH 0x00000080 ///< Port H Reset Control
-#define SYSCTL_SRCR2_GPIOG 0x00000040 ///< Port G Reset Control
-#define SYSCTL_SRCR2_GPIOF 0x00000020 ///< Port F Reset Control
-#define SYSCTL_SRCR2_GPIOE 0x00000010 ///< Port E Reset Control
-#define SYSCTL_SRCR2_GPIOD 0x00000008 ///< Port D Reset Control
-#define SYSCTL_SRCR2_GPIOC 0x00000004 ///< Port C Reset Control
-#define SYSCTL_SRCR2_GPIOB 0x00000002 ///< Port B Reset Control
-#define SYSCTL_SRCR2_GPIOA 0x00000001 ///< Port A Reset Control
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the SYSCTL_RIS register.
- */
-/*\{*/
-#define SYSCTL_RIS_PLLLRIS 0x00000040 ///< PLL Lock Raw Interrupt Status
-#define SYSCTL_RIS_BORRIS 0x00000002 ///< Brown-Out Reset Raw Interrupt
- ///< Status
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the SYSCTL_IMC register.
- */
-/*\{*/
-#define SYSCTL_IMC_PLLLIM 0x00000040 ///< PLL Lock Interrupt Mask
-#define SYSCTL_IMC_BORIM 0x00000002 ///< Brown-Out Reset Interrupt Mask
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the SYSCTL_MISC register.
- */
-/*\{*/
-#define SYSCTL_MISC_PLLLMIS 0x00000040 ///< PLL Lock Masked Interrupt Status
-#define SYSCTL_MISC_BORMIS 0x00000002 ///< BOR Masked Interrupt Status
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the SYSCTL_RESC register.
- */
-/*\{*/
-#define SYSCTL_RESC_SW 0x00000010 ///< Software Reset
-#define SYSCTL_RESC_WDT 0x00000008 ///< Watchdog Timer Reset
-#define SYSCTL_RESC_BOR 0x00000004 ///< Brown-Out Reset
-#define SYSCTL_RESC_POR 0x00000002 ///< Power-On Reset
-#define SYSCTL_RESC_EXT 0x00000001 ///< External Reset
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the SYSCTL_RCC register.
- */
-/*\{*/
-#define SYSCTL_RCC_ACG 0x08000000 ///< Auto Clock Gating
-#define SYSCTL_RCC_SYSDIV_M 0x07800000 ///< System Clock Divisor
-#define SYSCTL_RCC_SYSDIV_2 0x00800000 ///< System clock /2
-#define SYSCTL_RCC_SYSDIV_3 0x01000000 ///< System clock /3
-#define SYSCTL_RCC_SYSDIV_4 0x01800000 ///< System clock /4
-#define SYSCTL_RCC_SYSDIV_5 0x02000000 ///< System clock /5
-#define SYSCTL_RCC_SYSDIV_6 0x02800000 ///< System clock /6
-#define SYSCTL_RCC_SYSDIV_7 0x03000000 ///< System clock /7
-#define SYSCTL_RCC_SYSDIV_8 0x03800000 ///< System clock /8
-#define SYSCTL_RCC_SYSDIV_9 0x04000000 ///< System clock /9
-#define SYSCTL_RCC_SYSDIV_10 0x04800000 ///< System clock /10
-#define SYSCTL_RCC_SYSDIV_11 0x05000000 ///< System clock /11
-#define SYSCTL_RCC_SYSDIV_12 0x05800000 ///< System clock /12
-#define SYSCTL_RCC_SYSDIV_13 0x06000000 ///< System clock /13
-#define SYSCTL_RCC_SYSDIV_14 0x06800000 ///< System clock /14
-#define SYSCTL_RCC_SYSDIV_15 0x07000000 ///< System clock /15
-#define SYSCTL_RCC_SYSDIV_16 0x07800000 ///< System clock /16
-#define SYSCTL_RCC_USESYSDIV 0x00400000 ///< Enable System Clock Divider
-#define SYSCTL_RCC_USEPWMDIV 0x00100000 ///< Enable PWM Clock Divisor
-#define SYSCTL_RCC_PWMDIV_M 0x000E0000 ///< PWM Unit Clock Divisor
-#define SYSCTL_RCC_PWMDIV_2 0x00000000 ///< PWM clock /2
-#define SYSCTL_RCC_PWMDIV_4 0x00020000 ///< PWM clock /4
-#define SYSCTL_RCC_PWMDIV_8 0x00040000 ///< PWM clock /8
-#define SYSCTL_RCC_PWMDIV_16 0x00060000 ///< PWM clock /16
-#define SYSCTL_RCC_PWMDIV_32 0x00080000 ///< PWM clock /32
-#define SYSCTL_RCC_PWMDIV_64 0x000A0000 ///< PWM clock /64
-#define SYSCTL_RCC_PWRDN 0x00002000 ///< PLL Power Down
-#define SYSCTL_RCC_BYPASS 0x00000800 ///< PLL Bypass
-#define SYSCTL_RCC_XTAL_M 0x000003C0 ///< Crystal Value
-#define SYSCTL_RCC_XTAL_1MHZ 0x00000000 ///< 1 MHz
-#define SYSCTL_RCC_XTAL_1_84MHZ 0x00000040 ///< 1.8432 MHz
-#define SYSCTL_RCC_XTAL_2MHZ 0x00000080 ///< 2 MHz
-#define SYSCTL_RCC_XTAL_2_45MHZ 0x000000C0 ///< 2.4576 MHz
-#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 ///< 3.579545 MHz
-#define SYSCTL_RCC_XTAL_3_68MHZ 0x00000140 ///< 3.6864 MHz
-#define SYSCTL_RCC_XTAL_4MHZ 0x00000180 ///< 4 MHz
-#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 ///< 4.096 MHz
-#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 ///< 4.9152 MHz
-#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 ///< 5 MHz
-#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 ///< 5.12 MHz
-#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 ///< 6 MHz
-#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 ///< 6.144 MHz
-#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 ///< 7.3728 MHz
-#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 ///< 8 MHz
-#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 ///< 8.192 MHz
-#define SYSCTL_RCC_OSCSRC_M 0x00000030 ///< Oscillator Source
-#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 ///< MOSC
-#define SYSCTL_RCC_OSCSRC_INT 0x00000010 ///< IOSC
-#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 ///< IOSC/4
-#define SYSCTL_RCC_OSCSRC_30 0x00000030 ///< 30 kHz
-#define SYSCTL_RCC_IOSCDIS 0x00000002 ///< Internal Oscillator Disable
-#define SYSCTL_RCC_MOSCDIS 0x00000001 ///< Main Oscillator Disable
-#define SYSCTL_RCC_SYSDIV_S 23
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the SYSCTL_PLLCFG register.
- */
-/*\{*/
-#define SYSCTL_PLLCFG_F_M 0x00003FE0 ///< PLL F Value
-#define SYSCTL_PLLCFG_R_M 0x0000001F ///< PLL R Value
-#define SYSCTL_PLLCFG_F_S 5
-#define SYSCTL_PLLCFG_R_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the SYSCTL_RCC2 register.
- */
-/*\{*/
-#define SYSCTL_RCC2_USERCC2 0x80000000 ///< Use RCC2
-#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 ///< System Clock Divisor 2
-#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 ///< System clock /2
-#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 ///< System clock /3
-#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 ///< System clock /4
-#define SYSCTL_RCC2_SYSDIV2_5 0x02000000 ///< System clock /5
-#define SYSCTL_RCC2_SYSDIV2_6 0x02800000 ///< System clock /6
-#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 ///< System clock /7
-#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 ///< System clock /8
-#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 ///< System clock /9
-#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 ///< System clock /10
-#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 ///< System clock /11
-#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 ///< System clock /12
-#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 ///< System clock /13
-#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 ///< System clock /14
-#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 ///< System clock /15
-#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 ///< System clock /16
-#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 ///< System clock /17
-#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 ///< System clock /18
-#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 ///< System clock /19
-#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 ///< System clock /20
-#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 ///< System clock /21
-#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 ///< System clock /22
-#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 ///< System clock /23
-#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 ///< System clock /24
-#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 ///< System clock /25
-#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 ///< System clock /26
-#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 ///< System clock /27
-#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 ///< System clock /28
-#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 ///< System clock /29
-#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 ///< System clock /30
-#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 ///< System clock /31
-#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 ///< System clock /32
-#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 ///< System clock /33
-#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 ///< System clock /34
-#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 ///< System clock /35
-#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 ///< System clock /36
-#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 ///< System clock /37
-#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 ///< System clock /38
-#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 ///< System clock /39
-#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 ///< System clock /40
-#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 ///< System clock /41
-#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 ///< System clock /42
-#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 ///< System clock /43
-#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 ///< System clock /44
-#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 ///< System clock /45
-#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 ///< System clock /46
-#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 ///< System clock /47
-#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 ///< System clock /48
-#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 ///< System clock /49
-#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 ///< System clock /50
-#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 ///< System clock /51
-#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 ///< System clock /52
-#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 ///< System clock /53
-#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 ///< System clock /54
-#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 ///< System clock /55
-#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 ///< System clock /56
-#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 ///< System clock /57
-#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 ///< System clock /58
-#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 ///< System clock /59
-#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 ///< System clock /60
-#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 ///< System clock /61
-#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 ///< System clock /62
-#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 ///< System clock /63
-#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 ///< System clock /64
-#define SYSCTL_RCC2_PWRDN2 0x00002000 ///< Power-Down PLL 2
-#define SYSCTL_RCC2_BYPASS2 0x00000800 ///< PLL Bypass 2
-#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 ///< Oscillator Source 2
-#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 ///< MOSC
-#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 ///< PIOSC
-#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 ///< PIOSC/4
-#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 ///< 30 kHz
-#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 ///< 32.768 kHz
-#define SYSCTL_RCC2_SYSDIV2_S 23
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the SYSCTL_RCGC0 register.
- */
-/*\{*/
-#define SYSCTL_RCGC0_PWM 0x00100000 ///< PWM Clock Gating Control
-#define SYSCTL_RCGC0_ADC 0x00010000 ///< ADC0 Clock Gating Control
-#define SYSCTL_RCGC0_ADCSPD_M 0x00000300 ///< ADC Sample Speed
-#define SYSCTL_RCGC0_ADCSPD125K 0x00000000 ///< 125K samples/second
-#define SYSCTL_RCGC0_ADCSPD250K 0x00000100 ///< 250K samples/second
-#define SYSCTL_RCGC0_ADCSPD500K 0x00000200 ///< 500K samples/second
-#define SYSCTL_RCGC0_ADCSPD1M 0x00000300 ///< 1M samples/second
-#define SYSCTL_RCGC0_HIB 0x00000040 ///< HIB Clock Gating Control
-#define SYSCTL_RCGC0_WDT 0x00000008 ///< WDT Clock Gating Control
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the SYSCTL_RCGC1 register.
- */
-/*\{*/
-#define SYSCTL_RCGC1_COMP2 0x04000000 ///< Analog Comparator 2 Clock Gating
-#define SYSCTL_RCGC1_COMP1 0x02000000 ///< Analog Comparator 1 Clock Gating
-#define SYSCTL_RCGC1_COMP0 0x01000000 ///< Analog Comparator 0 Clock Gating
-#define SYSCTL_RCGC1_TIMER3 0x00080000 ///< Timer 3 Clock Gating Control
-#define SYSCTL_RCGC1_TIMER2 0x00040000 ///< Timer 2 Clock Gating Control
-#define SYSCTL_RCGC1_TIMER1 0x00020000 ///< Timer 1 Clock Gating Control
-#define SYSCTL_RCGC1_TIMER0 0x00010000 ///< Timer 0 Clock Gating Control
-#define SYSCTL_RCGC1_I2C1 0x00004000 ///< I2C1 Clock Gating Control
-#define SYSCTL_RCGC1_I2C0 0x00001000 ///< I2C0 Clock Gating Control
-#define SYSCTL_RCGC1_QEI1 0x00000200 ///< QEI1 Clock Gating Control
-#define SYSCTL_RCGC1_QEI0 0x00000100 ///< QEI0 Clock Gating Control
-#define SYSCTL_RCGC1_SSI1 0x00000020 ///< SSI1 Clock Gating Control
-#define SYSCTL_RCGC1_SSI0 0x00000010 ///< SSI0 Clock Gating Control
-#define SYSCTL_RCGC1_UART2 0x00000004 ///< UART2 Clock Gating Control
-#define SYSCTL_RCGC1_UART1 0x00000002 ///< UART1 Clock Gating Control
-#define SYSCTL_RCGC1_UART0 0x00000001 ///< UART0 Clock Gating Control
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the SYSCTL_RCGC2 register.
- */
-/*\{*/
-#define SYSCTL_RCGC2_GPIOH 0x00000080 ///< Port H Clock Gating Control
-#define SYSCTL_RCGC2_GPIOG 0x00000040 ///< Port G Clock Gating Control
-#define SYSCTL_RCGC2_GPIOF 0x00000020 ///< Port F Clock Gating Control
-#define SYSCTL_RCGC2_GPIOE 0x00000010 ///< Port E Clock Gating Control
-#define SYSCTL_RCGC2_GPIOD 0x00000008 ///< Port D Clock Gating Control
-#define SYSCTL_RCGC2_GPIOC 0x00000004 ///< Port C Clock Gating Control
-#define SYSCTL_RCGC2_GPIOB 0x00000002 ///< Port B Clock Gating Control
-#define SYSCTL_RCGC2_GPIOA 0x00000001 ///< Port A Clock Gating Control
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the SYSCTL_SCGC0 register.
- */
-/*\{*/
-#define SYSCTL_SCGC0_PWM 0x00100000 ///< PWM Clock Gating Control
-#define SYSCTL_SCGC0_ADC 0x00010000 ///< ADC0 Clock Gating Control
-#define SYSCTL_SCGC0_ADCSPD_M 0x00000300 ///< ADC Sample Speed
-#define SYSCTL_SCGC0_ADCSPD125K 0x00000000 ///< 125K samples/second
-#define SYSCTL_SCGC0_ADCSPD250K 0x00000100 ///< 250K samples/second
-#define SYSCTL_SCGC0_ADCSPD500K 0x00000200 ///< 500K samples/second
-#define SYSCTL_SCGC0_ADCSPD1M 0x00000300 ///< 1M samples/second
-#define SYSCTL_SCGC0_HIB 0x00000040 ///< HIB Clock Gating Control
-#define SYSCTL_SCGC0_WDT 0x00000008 ///< WDT Clock Gating Control
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the SYSCTL_SCGC1 register.
- */
-/*\{*/
-#define SYSCTL_SCGC1_COMP2 0x04000000 ///< Analog Comparator 2 Clock Gating
-#define SYSCTL_SCGC1_COMP1 0x02000000 ///< Analog Comparator 1 Clock Gating
-#define SYSCTL_SCGC1_COMP0 0x01000000 ///< Analog Comparator 0 Clock Gating
-#define SYSCTL_SCGC1_TIMER3 0x00080000 ///< Timer 3 Clock Gating Control
-#define SYSCTL_SCGC1_TIMER2 0x00040000 ///< Timer 2 Clock Gating Control
-#define SYSCTL_SCGC1_TIMER1 0x00020000 ///< Timer 1 Clock Gating Control
-#define SYSCTL_SCGC1_TIMER0 0x00010000 ///< Timer 0 Clock Gating Control
-#define SYSCTL_SCGC1_I2C1 0x00004000 ///< I2C1 Clock Gating Control
-#define SYSCTL_SCGC1_I2C0 0x00001000 ///< I2C0 Clock Gating Control
-#define SYSCTL_SCGC1_QEI1 0x00000200 ///< QEI1 Clock Gating Control
-#define SYSCTL_SCGC1_QEI0 0x00000100 ///< QEI0 Clock Gating Control
-#define SYSCTL_SCGC1_SSI1 0x00000020 ///< SSI1 Clock Gating Control
-#define SYSCTL_SCGC1_SSI0 0x00000010 ///< SSI0 Clock Gating Control
-#define SYSCTL_SCGC1_UART2 0x00000004 ///< UART2 Clock Gating Control
-#define SYSCTL_SCGC1_UART1 0x00000002 ///< UART1 Clock Gating Control
-#define SYSCTL_SCGC1_UART0 0x00000001 ///< UART0 Clock Gating Control
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the SYSCTL_SCGC2 register.
- */
-/*\{*/
-#define SYSCTL_SCGC2_GPIOH 0x00000080 ///< Port H Clock Gating Control
-#define SYSCTL_SCGC2_GPIOG 0x00000040 ///< Port G Clock Gating Control
-#define SYSCTL_SCGC2_GPIOF 0x00000020 ///< Port F Clock Gating Control
-#define SYSCTL_SCGC2_GPIOE 0x00000010 ///< Port E Clock Gating Control
-#define SYSCTL_SCGC2_GPIOD 0x00000008 ///< Port D Clock Gating Control
-#define SYSCTL_SCGC2_GPIOC 0x00000004 ///< Port C Clock Gating Control
-#define SYSCTL_SCGC2_GPIOB 0x00000002 ///< Port B Clock Gating Control
-#define SYSCTL_SCGC2_GPIOA 0x00000001 ///< Port A Clock Gating Control
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the SYSCTL_DCGC0 register.
- */
-/*\{*/
-#define SYSCTL_DCGC0_PWM 0x00100000 ///< PWM Clock Gating Control
-#define SYSCTL_DCGC0_ADC 0x00010000 ///< ADC0 Clock Gating Control
-#define SYSCTL_DCGC0_HIB 0x00000040 ///< HIB Clock Gating Control
-#define SYSCTL_DCGC0_WDT 0x00000008 ///< WDT Clock Gating Control
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the SYSCTL_DCGC1 register.
- */
-/*\{*/
-#define SYSCTL_DCGC1_COMP2 0x04000000 ///< Analog Comparator 2 Clock Gating
-#define SYSCTL_DCGC1_COMP1 0x02000000 ///< Analog Comparator 1 Clock Gating
-#define SYSCTL_DCGC1_COMP0 0x01000000 ///< Analog Comparator 0 Clock Gating
-#define SYSCTL_DCGC1_TIMER3 0x00080000 ///< Timer 3 Clock Gating Control
-#define SYSCTL_DCGC1_TIMER2 0x00040000 ///< Timer 2 Clock Gating Control
-#define SYSCTL_DCGC1_TIMER1 0x00020000 ///< Timer 1 Clock Gating Control
-#define SYSCTL_DCGC1_TIMER0 0x00010000 ///< Timer 0 Clock Gating Control
-#define SYSCTL_DCGC1_I2C1 0x00004000 ///< I2C1 Clock Gating Control
-#define SYSCTL_DCGC1_I2C0 0x00001000 ///< I2C0 Clock Gating Control
-#define SYSCTL_DCGC1_QEI1 0x00000200 ///< QEI1 Clock Gating Control
-#define SYSCTL_DCGC1_QEI0 0x00000100 ///< QEI0 Clock Gating Control
-#define SYSCTL_DCGC1_SSI1 0x00000020 ///< SSI1 Clock Gating Control
-#define SYSCTL_DCGC1_SSI0 0x00000010 ///< SSI0 Clock Gating Control
-#define SYSCTL_DCGC1_UART2 0x00000004 ///< UART2 Clock Gating Control
-#define SYSCTL_DCGC1_UART1 0x00000002 ///< UART1 Clock Gating Control
-#define SYSCTL_DCGC1_UART0 0x00000001 ///< UART0 Clock Gating Control
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the SYSCTL_DCGC2 register.
- */
-/*\{*/
-#define SYSCTL_DCGC2_GPIOH 0x00000080 ///< Port H Clock Gating Control
-#define SYSCTL_DCGC2_GPIOG 0x00000040 ///< Port G Clock Gating Control
-#define SYSCTL_DCGC2_GPIOF 0x00000020 ///< Port F Clock Gating Control
-#define SYSCTL_DCGC2_GPIOE 0x00000010 ///< Port E Clock Gating Control
-#define SYSCTL_DCGC2_GPIOD 0x00000008 ///< Port D Clock Gating Control
-#define SYSCTL_DCGC2_GPIOC 0x00000004 ///< Port C Clock Gating Control
-#define SYSCTL_DCGC2_GPIOB 0x00000002 ///< Port B Clock Gating Control
-#define SYSCTL_DCGC2_GPIOA 0x00000001 ///< Port A Clock Gating Control
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG
-* register.
- */
-/*\{*/
-#define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 ///< Divider Field Override
-#define SYSCTL_DSLPCLKCFG_D_1 0x00000000 ///< System clock /1
-#define SYSCTL_DSLPCLKCFG_D_2 0x00800000 ///< System clock /2
-#define SYSCTL_DSLPCLKCFG_D_3 0x01000000 ///< System clock /3
-#define SYSCTL_DSLPCLKCFG_D_4 0x01800000 ///< System clock /4
-#define SYSCTL_DSLPCLKCFG_D_5 0x02000000 ///< System clock /5
-#define SYSCTL_DSLPCLKCFG_D_6 0x02800000 ///< System clock /6
-#define SYSCTL_DSLPCLKCFG_D_7 0x03000000 ///< System clock /7
-#define SYSCTL_DSLPCLKCFG_D_8 0x03800000 ///< System clock /8
-#define SYSCTL_DSLPCLKCFG_D_9 0x04000000 ///< System clock /9
-#define SYSCTL_DSLPCLKCFG_D_10 0x04800000 ///< System clock /10
-#define SYSCTL_DSLPCLKCFG_D_11 0x05000000 ///< System clock /11
-#define SYSCTL_DSLPCLKCFG_D_12 0x05800000 ///< System clock /12
-#define SYSCTL_DSLPCLKCFG_D_13 0x06000000 ///< System clock /13
-#define SYSCTL_DSLPCLKCFG_D_14 0x06800000 ///< System clock /14
-#define SYSCTL_DSLPCLKCFG_D_15 0x07000000 ///< System clock /15
-#define SYSCTL_DSLPCLKCFG_D_16 0x07800000 ///< System clock /16
-#define SYSCTL_DSLPCLKCFG_D_17 0x08000000 ///< System clock /17
-#define SYSCTL_DSLPCLKCFG_D_18 0x08800000 ///< System clock /18
-#define SYSCTL_DSLPCLKCFG_D_19 0x09000000 ///< System clock /19
-#define SYSCTL_DSLPCLKCFG_D_20 0x09800000 ///< System clock /20
-#define SYSCTL_DSLPCLKCFG_D_21 0x0A000000 ///< System clock /21
-#define SYSCTL_DSLPCLKCFG_D_22 0x0A800000 ///< System clock /22
-#define SYSCTL_DSLPCLKCFG_D_23 0x0B000000 ///< System clock /23
-#define SYSCTL_DSLPCLKCFG_D_24 0x0B800000 ///< System clock /24
-#define SYSCTL_DSLPCLKCFG_D_25 0x0C000000 ///< System clock /25
-#define SYSCTL_DSLPCLKCFG_D_26 0x0C800000 ///< System clock /26
-#define SYSCTL_DSLPCLKCFG_D_27 0x0D000000 ///< System clock /27
-#define SYSCTL_DSLPCLKCFG_D_28 0x0D800000 ///< System clock /28
-#define SYSCTL_DSLPCLKCFG_D_29 0x0E000000 ///< System clock /29
-#define SYSCTL_DSLPCLKCFG_D_30 0x0E800000 ///< System clock /30
-#define SYSCTL_DSLPCLKCFG_D_31 0x0F000000 ///< System clock /31
-#define SYSCTL_DSLPCLKCFG_D_32 0x0F800000 ///< System clock /32
-#define SYSCTL_DSLPCLKCFG_D_33 0x10000000 ///< System clock /33
-#define SYSCTL_DSLPCLKCFG_D_34 0x10800000 ///< System clock /34
-#define SYSCTL_DSLPCLKCFG_D_35 0x11000000 ///< System clock /35
-#define SYSCTL_DSLPCLKCFG_D_36 0x11800000 ///< System clock /36
-#define SYSCTL_DSLPCLKCFG_D_37 0x12000000 ///< System clock /37
-#define SYSCTL_DSLPCLKCFG_D_38 0x12800000 ///< System clock /38
-#define SYSCTL_DSLPCLKCFG_D_39 0x13000000 ///< System clock /39
-#define SYSCTL_DSLPCLKCFG_D_40 0x13800000 ///< System clock /40
-#define SYSCTL_DSLPCLKCFG_D_41 0x14000000 ///< System clock /41
-#define SYSCTL_DSLPCLKCFG_D_42 0x14800000 ///< System clock /42
-#define SYSCTL_DSLPCLKCFG_D_43 0x15000000 ///< System clock /43
-#define SYSCTL_DSLPCLKCFG_D_44 0x15800000 ///< System clock /44
-#define SYSCTL_DSLPCLKCFG_D_45 0x16000000 ///< System clock /45
-#define SYSCTL_DSLPCLKCFG_D_46 0x16800000 ///< System clock /46
-#define SYSCTL_DSLPCLKCFG_D_47 0x17000000 ///< System clock /47
-#define SYSCTL_DSLPCLKCFG_D_48 0x17800000 ///< System clock /48
-#define SYSCTL_DSLPCLKCFG_D_49 0x18000000 ///< System clock /49
-#define SYSCTL_DSLPCLKCFG_D_50 0x18800000 ///< System clock /50
-#define SYSCTL_DSLPCLKCFG_D_51 0x19000000 ///< System clock /51
-#define SYSCTL_DSLPCLKCFG_D_52 0x19800000 ///< System clock /52
-#define SYSCTL_DSLPCLKCFG_D_53 0x1A000000 ///< System clock /53
-#define SYSCTL_DSLPCLKCFG_D_54 0x1A800000 ///< System clock /54
-#define SYSCTL_DSLPCLKCFG_D_55 0x1B000000 ///< System clock /55
-#define SYSCTL_DSLPCLKCFG_D_56 0x1B800000 ///< System clock /56
-#define SYSCTL_DSLPCLKCFG_D_57 0x1C000000 ///< System clock /57
-#define SYSCTL_DSLPCLKCFG_D_58 0x1C800000 ///< System clock /58
-#define SYSCTL_DSLPCLKCFG_D_59 0x1D000000 ///< System clock /59
-#define SYSCTL_DSLPCLKCFG_D_60 0x1D800000 ///< System clock /60
-#define SYSCTL_DSLPCLKCFG_D_61 0x1E000000 ///< System clock /61
-#define SYSCTL_DSLPCLKCFG_D_62 0x1E800000 ///< System clock /62
-#define SYSCTL_DSLPCLKCFG_D_63 0x1F000000 ///< System clock /63
-#define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 ///< System clock /64
-#define SYSCTL_DSLPCLKCFG_O_M 0x00000070 ///< Clock Source
-#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 ///< MOSC
-#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 ///< PIOSC
-#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 ///< 30 kHz
-#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 ///< 32.768 kHz
-#define SYSCTL_DSLPCLKCFG_D_S 23
-/*\}*/
-
/**
* The following are defines for the bit fields in the NVIC_INT_TYPE register.
*/
projects / bertos.git / blobdiff