#define TIMER_TBR_TBRL_S 0
/*\}*/
-/**
- * The following are defines for the bit fields in the ADC_O_ACTSS register.
- */
-/*\{*/
-#define ADC_ACTSS_ASEN3 0x00000008 ///< ADC SS3 Enable
-#define ADC_ACTSS_ASEN2 0x00000004 ///< ADC SS2 Enable
-#define ADC_ACTSS_ASEN1 0x00000002 ///< ADC SS1 Enable
-#define ADC_ACTSS_ASEN0 0x00000001 ///< ADC SS0 Enable
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the ADC_O_RIS register.
- */
-/*\{*/
-#define ADC_RIS_INR3 0x00000008 ///< SS3 Raw Interrupt Status
-#define ADC_RIS_INR2 0x00000004 ///< SS2 Raw Interrupt Status
-#define ADC_RIS_INR1 0x00000002 ///< SS1 Raw Interrupt Status
-#define ADC_RIS_INR0 0x00000001 ///< SS0 Raw Interrupt Status
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the ADC_O_IM register.
- */
-/*\{*/
-#define ADC_IM_MASK3 0x00000008 ///< SS3 Interrupt Mask
-#define ADC_IM_MASK2 0x00000004 ///< SS2 Interrupt Mask
-#define ADC_IM_MASK1 0x00000002 ///< SS1 Interrupt Mask
-#define ADC_IM_MASK0 0x00000001 ///< SS0 Interrupt Mask
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the ADC_O_ISC register.
- */
-/*\{*/
-#define ADC_ISC_IN3 0x00000008 ///< SS3 Interrupt Status and Clear
-#define ADC_ISC_IN2 0x00000004 ///< SS2 Interrupt Status and Clear
-#define ADC_ISC_IN1 0x00000002 ///< SS1 Interrupt Status and Clear
-#define ADC_ISC_IN0 0x00000001 ///< SS0 Interrupt Status and Clear
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the ADC_O_OSTAT register.
- */
-/*\{*/
-#define ADC_OSTAT_OV3 0x00000008 ///< SS3 FIFO Overflow
-#define ADC_OSTAT_OV2 0x00000004 ///< SS2 FIFO Overflow
-#define ADC_OSTAT_OV1 0x00000002 ///< SS1 FIFO Overflow
-#define ADC_OSTAT_OV0 0x00000001 ///< SS0 FIFO Overflow
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the ADC_O_EMUX register.
- */
-/*\{*/
-#define ADC_EMUX_EM3_M 0x0000F000 ///< SS3 Trigger Select
-#define ADC_EMUX_EM3_PROCESSOR 0x00000000 ///< Processor (default)
-#define ADC_EMUX_EM3_COMP0 0x00001000 ///< Analog Comparator 0
-#define ADC_EMUX_EM3_COMP1 0x00002000 ///< Analog Comparator 1
-#define ADC_EMUX_EM3_COMP2 0x00003000 ///< Analog Comparator 2
-#define ADC_EMUX_EM3_EXTERNAL 0x00004000 ///< External (GPIO PB4)
-#define ADC_EMUX_EM3_TIMER 0x00005000 ///< Timer
-#define ADC_EMUX_EM3_PWM0 0x00006000 ///< PWM0
-#define ADC_EMUX_EM3_PWM1 0x00007000 ///< PWM1
-#define ADC_EMUX_EM3_PWM2 0x00008000 ///< PWM2
-#define ADC_EMUX_EM3_ALWAYS 0x0000F000 ///< Always (continuously sample)
-#define ADC_EMUX_EM2_M 0x00000F00 ///< SS2 Trigger Select
-#define ADC_EMUX_EM2_PROCESSOR 0x00000000 ///< Processor (default)
-#define ADC_EMUX_EM2_COMP0 0x00000100 ///< Analog Comparator 0
-#define ADC_EMUX_EM2_COMP1 0x00000200 ///< Analog Comparator 1
-#define ADC_EMUX_EM2_COMP2 0x00000300 ///< Analog Comparator 2
-#define ADC_EMUX_EM2_EXTERNAL 0x00000400 ///< External (GPIO PB4)
-#define ADC_EMUX_EM2_TIMER 0x00000500 ///< Timer
-#define ADC_EMUX_EM2_PWM0 0x00000600 ///< PWM0
-#define ADC_EMUX_EM2_PWM1 0x00000700 ///< PWM1
-#define ADC_EMUX_EM2_PWM2 0x00000800 ///< PWM2
-#define ADC_EMUX_EM2_ALWAYS 0x00000F00 ///< Always (continuously sample)
-#define ADC_EMUX_EM1_M 0x000000F0 ///< SS1 Trigger Select
-#define ADC_EMUX_EM1_PROCESSOR 0x00000000 ///< Processor (default)
-#define ADC_EMUX_EM1_COMP0 0x00000010 ///< Analog Comparator 0
-#define ADC_EMUX_EM1_COMP1 0x00000020 ///< Analog Comparator 1
-#define ADC_EMUX_EM1_COMP2 0x00000030 ///< Analog Comparator 2
-#define ADC_EMUX_EM1_EXTERNAL 0x00000040 ///< External (GPIO PB4)
-#define ADC_EMUX_EM1_TIMER 0x00000050 ///< Timer
-#define ADC_EMUX_EM1_PWM0 0x00000060 ///< PWM0
-#define ADC_EMUX_EM1_PWM1 0x00000070 ///< PWM1
-#define ADC_EMUX_EM1_PWM2 0x00000080 ///< PWM2
-#define ADC_EMUX_EM1_ALWAYS 0x000000F0 ///< Always (continuously sample)
-#define ADC_EMUX_EM0_M 0x0000000F ///< SS0 Trigger Select
-#define ADC_EMUX_EM0_PROCESSOR 0x00000000 ///< Processor (default)
-#define ADC_EMUX_EM0_COMP0 0x00000001 ///< Analog Comparator 0
-#define ADC_EMUX_EM0_COMP1 0x00000002 ///< Analog Comparator 1
-#define ADC_EMUX_EM0_COMP2 0x00000003 ///< Analog Comparator 2
-#define ADC_EMUX_EM0_EXTERNAL 0x00000004 ///< External (GPIO PB4)
-#define ADC_EMUX_EM0_TIMER 0x00000005 ///< Timer
-#define ADC_EMUX_EM0_PWM0 0x00000006 ///< PWM0
-#define ADC_EMUX_EM0_PWM1 0x00000007 ///< PWM1
-#define ADC_EMUX_EM0_PWM2 0x00000008 ///< PWM2
-#define ADC_EMUX_EM0_ALWAYS 0x0000000F ///< Always (continuously sample)
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the ADC_O_USTAT register.
- */
-/*\{*/
-#define ADC_USTAT_UV3 0x00000008 ///< SS3 FIFO Underflow
-#define ADC_USTAT_UV2 0x00000004 ///< SS2 FIFO Underflow
-#define ADC_USTAT_UV1 0x00000002 ///< SS1 FIFO Underflow
-#define ADC_USTAT_UV0 0x00000001 ///< SS0 FIFO Underflow
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the ADC_O_SSPRI register.
- */
-/*\{*/
-#define ADC_SSPRI_SS3_M 0x00003000 ///< SS3 Priority
-#define ADC_SSPRI_SS3_1ST 0x00000000 ///< First priority
-#define ADC_SSPRI_SS3_2ND 0x00001000 ///< Second priority
-#define ADC_SSPRI_SS3_3RD 0x00002000 ///< Third priority
-#define ADC_SSPRI_SS3_4TH 0x00003000 ///< Fourth priority
-#define ADC_SSPRI_SS2_M 0x00000300 ///< SS2 Priority
-#define ADC_SSPRI_SS2_1ST 0x00000000 ///< First priority
-#define ADC_SSPRI_SS2_2ND 0x00000100 ///< Second priority
-#define ADC_SSPRI_SS2_3RD 0x00000200 ///< Third priority
-#define ADC_SSPRI_SS2_4TH 0x00000300 ///< Fourth priority
-#define ADC_SSPRI_SS1_M 0x00000030 ///< SS1 Priority
-#define ADC_SSPRI_SS1_1ST 0x00000000 ///< First priority
-#define ADC_SSPRI_SS1_2ND 0x00000010 ///< Second priority
-#define ADC_SSPRI_SS1_3RD 0x00000020 ///< Third priority
-#define ADC_SSPRI_SS1_4TH 0x00000030 ///< Fourth priority
-#define ADC_SSPRI_SS0_M 0x00000003 ///< SS0 Priority
-#define ADC_SSPRI_SS0_1ST 0x00000000 ///< First priority
-#define ADC_SSPRI_SS0_2ND 0x00000001 ///< Second priority
-#define ADC_SSPRI_SS0_3RD 0x00000002 ///< Third priority
-#define ADC_SSPRI_SS0_4TH 0x00000003 ///< Fourth priority
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the ADC_O_PSSI register.
- */
-/*\{*/
-#define ADC_PSSI_SS3 0x00000008 ///< SS3 Initiate
-#define ADC_PSSI_SS2 0x00000004 ///< SS2 Initiate
-#define ADC_PSSI_SS1 0x00000002 ///< SS1 Initiate
-#define ADC_PSSI_SS0 0x00000001 ///< SS0 Initiate
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the ADC_O_SAC register.
- */
-/*\{*/
-#define ADC_SAC_AVG_M 0x00000007 ///< Hardware Averaging Control
-#define ADC_SAC_AVG_OFF 0x00000000 ///< No hardware oversampling
-#define ADC_SAC_AVG_2X 0x00000001 ///< 2x hardware oversampling
-#define ADC_SAC_AVG_4X 0x00000002 ///< 4x hardware oversampling
-#define ADC_SAC_AVG_8X 0x00000003 ///< 8x hardware oversampling
-#define ADC_SAC_AVG_16X 0x00000004 ///< 16x hardware oversampling
-#define ADC_SAC_AVG_32X 0x00000005 ///< 32x hardware oversampling
-#define ADC_SAC_AVG_64X 0x00000006 ///< 64x hardware oversampling
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the ADC_O_SSMUX0 register.
- */
-/*\{*/
-#define ADC_SSMUX0_MUX7_M 0x70000000 ///< 8th Sample Input Select
-#define ADC_SSMUX0_MUX6_M 0x07000000 ///< 7th Sample Input Select
-#define ADC_SSMUX0_MUX5_M 0x00700000 ///< 6th Sample Input Select
-#define ADC_SSMUX0_MUX4_M 0x00070000 ///< 5th Sample Input Select
-#define ADC_SSMUX0_MUX3_M 0x00007000 ///< 4th Sample Input Select
-#define ADC_SSMUX0_MUX2_M 0x00000700 ///< 3rd Sample Input Select
-#define ADC_SSMUX0_MUX1_M 0x00000070 ///< 2nd Sample Input Select
-#define ADC_SSMUX0_MUX0_M 0x00000007 ///< 1st Sample Input Select
-#define ADC_SSMUX0_MUX7_S 28
-#define ADC_SSMUX0_MUX6_S 24
-#define ADC_SSMUX0_MUX5_S 20
-#define ADC_SSMUX0_MUX4_S 16
-#define ADC_SSMUX0_MUX3_S 12
-#define ADC_SSMUX0_MUX2_S 8
-#define ADC_SSMUX0_MUX1_S 4
-#define ADC_SSMUX0_MUX0_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the ADC_O_SSCTL0 register.
- */
-/*\{*/
-#define ADC_SSCTL0_TS7 0x80000000 ///< 8th Sample Temp Sensor Select
-#define ADC_SSCTL0_IE7 0x40000000 ///< 8th Sample Interrupt Enable
-#define ADC_SSCTL0_END7 0x20000000 ///< 8th Sample is End of Sequence
-#define ADC_SSCTL0_D7 0x10000000 ///< 8th Sample Diff Input Select
-#define ADC_SSCTL0_TS6 0x08000000 ///< 7th Sample Temp Sensor Select
-#define ADC_SSCTL0_IE6 0x04000000 ///< 7th Sample Interrupt Enable
-#define ADC_SSCTL0_END6 0x02000000 ///< 7th Sample is End of Sequence
-#define ADC_SSCTL0_D6 0x01000000 ///< 7th Sample Diff Input Select
-#define ADC_SSCTL0_TS5 0x00800000 ///< 6th Sample Temp Sensor Select
-#define ADC_SSCTL0_IE5 0x00400000 ///< 6th Sample Interrupt Enable
-#define ADC_SSCTL0_END5 0x00200000 ///< 6th Sample is End of Sequence
-#define ADC_SSCTL0_D5 0x00100000 ///< 6th Sample Diff Input Select
-#define ADC_SSCTL0_TS4 0x00080000 ///< 5th Sample Temp Sensor Select
-#define ADC_SSCTL0_IE4 0x00040000 ///< 5th Sample Interrupt Enable
-#define ADC_SSCTL0_END4 0x00020000 ///< 5th Sample is End of Sequence
-#define ADC_SSCTL0_D4 0x00010000 ///< 5th Sample Diff Input Select
-#define ADC_SSCTL0_TS3 0x00008000 ///< 4th Sample Temp Sensor Select
-#define ADC_SSCTL0_IE3 0x00004000 ///< 4th Sample Interrupt Enable
-#define ADC_SSCTL0_END3 0x00002000 ///< 4th Sample is End of Sequence
-#define ADC_SSCTL0_D3 0x00001000 ///< 4th Sample Diff Input Select
-#define ADC_SSCTL0_TS2 0x00000800 ///< 3rd Sample Temp Sensor Select
-#define ADC_SSCTL0_IE2 0x00000400 ///< 3rd Sample Interrupt Enable
-#define ADC_SSCTL0_END2 0x00000200 ///< 3rd Sample is End of Sequence
-#define ADC_SSCTL0_D2 0x00000100 ///< 3rd Sample Diff Input Select
-#define ADC_SSCTL0_TS1 0x00000080 ///< 2nd Sample Temp Sensor Select
-#define ADC_SSCTL0_IE1 0x00000040 ///< 2nd Sample Interrupt Enable
-#define ADC_SSCTL0_END1 0x00000020 ///< 2nd Sample is End of Sequence
-#define ADC_SSCTL0_D1 0x00000010 ///< 2nd Sample Diff Input Select
-#define ADC_SSCTL0_TS0 0x00000008 ///< 1st Sample Temp Sensor Select
-#define ADC_SSCTL0_IE0 0x00000004 ///< 1st Sample Interrupt Enable
-#define ADC_SSCTL0_END0 0x00000002 ///< 1st Sample is End of Sequence
-#define ADC_SSCTL0_D0 0x00000001 ///< 1st Sample Diff Input Select
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
- */
-/*\{*/
-#define ADC_SSFIFO0_DATA_M 0x000003FF ///< Conversion Result Data
-#define ADC_SSFIFO0_DATA_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
- */
-/*\{*/
-#define ADC_SSFSTAT0_FULL 0x00001000 ///< FIFO Full
-#define ADC_SSFSTAT0_EMPTY 0x00000100 ///< FIFO Empty
-#define ADC_SSFSTAT0_HPTR_M 0x000000F0 ///< FIFO Head Pointer
-#define ADC_SSFSTAT0_TPTR_M 0x0000000F ///< FIFO Tail Pointer
-#define ADC_SSFSTAT0_HPTR_S 4
-#define ADC_SSFSTAT0_TPTR_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the ADC_O_SSMUX1 register.
- */
-/*\{*/
-#define ADC_SSMUX1_MUX3_M 0x00007000 ///< 4th Sample Input Select
-#define ADC_SSMUX1_MUX2_M 0x00000700 ///< 3rd Sample Input Select
-#define ADC_SSMUX1_MUX1_M 0x00000070 ///< 2nd Sample Input Select
-#define ADC_SSMUX1_MUX0_M 0x00000007 ///< 1st Sample Input Select
-#define ADC_SSMUX1_MUX3_S 12
-#define ADC_SSMUX1_MUX2_S 8
-#define ADC_SSMUX1_MUX1_S 4
-#define ADC_SSMUX1_MUX0_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the ADC_O_SSCTL1 register.
- */
-/*\{*/
-#define ADC_SSCTL1_TS3 0x00008000 ///< 4th Sample Temp Sensor Select
-#define ADC_SSCTL1_IE3 0x00004000 ///< 4th Sample Interrupt Enable
-#define ADC_SSCTL1_END3 0x00002000 ///< 4th Sample is End of Sequence
-#define ADC_SSCTL1_D3 0x00001000 ///< 4th Sample Diff Input Select
-#define ADC_SSCTL1_TS2 0x00000800 ///< 3rd Sample Temp Sensor Select
-#define ADC_SSCTL1_IE2 0x00000400 ///< 3rd Sample Interrupt Enable
-#define ADC_SSCTL1_END2 0x00000200 ///< 3rd Sample is End of Sequence
-#define ADC_SSCTL1_D2 0x00000100 ///< 3rd Sample Diff Input Select
-#define ADC_SSCTL1_TS1 0x00000080 ///< 2nd Sample Temp Sensor Select
-#define ADC_SSCTL1_IE1 0x00000040 ///< 2nd Sample Interrupt Enable
-#define ADC_SSCTL1_END1 0x00000020 ///< 2nd Sample is End of Sequence
-#define ADC_SSCTL1_D1 0x00000010 ///< 2nd Sample Diff Input Select
-#define ADC_SSCTL1_TS0 0x00000008 ///< 1st Sample Temp Sensor Select
-#define ADC_SSCTL1_IE0 0x00000004 ///< 1st Sample Interrupt Enable
-#define ADC_SSCTL1_END0 0x00000002 ///< 1st Sample is End of Sequence
-#define ADC_SSCTL1_D0 0x00000001 ///< 1st Sample Diff Input Select
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
- */
-/*\{*/
-#define ADC_SSFIFO1_DATA_M 0x000003FF ///< Conversion Result Data
-#define ADC_SSFIFO1_DATA_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
- */
-/*\{*/
-#define ADC_SSFSTAT1_FULL 0x00001000 ///< FIFO Full
-#define ADC_SSFSTAT1_EMPTY 0x00000100 ///< FIFO Empty
-#define ADC_SSFSTAT1_HPTR_M 0x000000F0 ///< FIFO Head Pointer
-#define ADC_SSFSTAT1_TPTR_M 0x0000000F ///< FIFO Tail Pointer
-#define ADC_SSFSTAT1_HPTR_S 4
-#define ADC_SSFSTAT1_TPTR_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the ADC_O_SSMUX2 register.
- */
-/*\{*/
-#define ADC_SSMUX2_MUX3_M 0x00007000 ///< 4th Sample Input Select
-#define ADC_SSMUX2_MUX2_M 0x00000700 ///< 3rd Sample Input Select
-#define ADC_SSMUX2_MUX1_M 0x00000070 ///< 2nd Sample Input Select
-#define ADC_SSMUX2_MUX0_M 0x00000007 ///< 1st Sample Input Select
-#define ADC_SSMUX2_MUX3_S 12
-#define ADC_SSMUX2_MUX2_S 8
-#define ADC_SSMUX2_MUX1_S 4
-#define ADC_SSMUX2_MUX0_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the ADC_O_SSCTL2 register.
- */
-/*\{*/
-#define ADC_SSCTL2_TS3 0x00008000 ///< 4th Sample Temp Sensor Select
-#define ADC_SSCTL2_IE3 0x00004000 ///< 4th Sample Interrupt Enable
-#define ADC_SSCTL2_END3 0x00002000 ///< 4th Sample is End of Sequence
-#define ADC_SSCTL2_D3 0x00001000 ///< 4th Sample Diff Input Select
-#define ADC_SSCTL2_TS2 0x00000800 ///< 3rd Sample Temp Sensor Select
-#define ADC_SSCTL2_IE2 0x00000400 ///< 3rd Sample Interrupt Enable
-#define ADC_SSCTL2_END2 0x00000200 ///< 3rd Sample is End of Sequence
-#define ADC_SSCTL2_D2 0x00000100 ///< 3rd Sample Diff Input Select
-#define ADC_SSCTL2_TS1 0x00000080 ///< 2nd Sample Temp Sensor Select
-#define ADC_SSCTL2_IE1 0x00000040 ///< 2nd Sample Interrupt Enable
-#define ADC_SSCTL2_END1 0x00000020 ///< 2nd Sample is End of Sequence
-#define ADC_SSCTL2_D1 0x00000010 ///< 2nd Sample Diff Input Select
-#define ADC_SSCTL2_TS0 0x00000008 ///< 1st Sample Temp Sensor Select
-#define ADC_SSCTL2_IE0 0x00000004 ///< 1st Sample Interrupt Enable
-#define ADC_SSCTL2_END0 0x00000002 ///< 1st Sample is End of Sequence
-#define ADC_SSCTL2_D0 0x00000001 ///< 1st Sample Diff Input Select
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
- */
-/*\{*/
-#define ADC_SSFIFO2_DATA_M 0x000003FF ///< Conversion Result Data
-#define ADC_SSFIFO2_DATA_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
- */
-/*\{*/
-#define ADC_SSFSTAT2_FULL 0x00001000 ///< FIFO Full
-#define ADC_SSFSTAT2_EMPTY 0x00000100 ///< FIFO Empty
-#define ADC_SSFSTAT2_HPTR_M 0x000000F0 ///< FIFO Head Pointer
-#define ADC_SSFSTAT2_TPTR_M 0x0000000F ///< FIFO Tail Pointer
-#define ADC_SSFSTAT2_HPTR_S 4
-#define ADC_SSFSTAT2_TPTR_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the ADC_O_SSMUX3 register.
- */
-/*\{*/
-#define ADC_SSMUX3_MUX0_M 0x00000007 ///< 1st Sample Input Select
-#define ADC_SSMUX3_MUX0_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the ADC_O_SSCTL3 register.
- */
-/*\{*/
-#define ADC_SSCTL3_TS0 0x00000008 ///< 1st Sample Temp Sensor Select
-#define ADC_SSCTL3_IE0 0x00000004 ///< 1st Sample Interrupt Enable
-#define ADC_SSCTL3_END0 0x00000002 ///< 1st Sample is End of Sequence
-#define ADC_SSCTL3_D0 0x00000001 ///< 1st Sample Diff Input Select
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
- */
-/*\{*/
-#define ADC_SSFIFO3_DATA_M 0x000003FF ///< Conversion Result Data
-#define ADC_SSFIFO3_DATA_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
- */
-/*\{*/
-#define ADC_SSFSTAT3_FULL 0x00001000 ///< FIFO Full
-#define ADC_SSFSTAT3_EMPTY 0x00000100 ///< FIFO Empty
-#define ADC_SSFSTAT3_HPTR_M 0x000000F0 ///< FIFO Head Pointer
-#define ADC_SSFSTAT3_TPTR_M 0x0000000F ///< FIFO Tail Pointer
-#define ADC_SSFSTAT3_HPTR_S 4
-#define ADC_SSFSTAT3_TPTR_S 0
-/*\}*/
-
-/**
- * The following are defines for the bit fields in the ADC_O_TMLB register.
- */
-/*\{*/
-#define ADC_TMLB_LB 0x00000001 ///< Loopback Mode Enable
-/*\}*/
-
-/**
- * The following are defines for the the interpretation of the data in the
-* SSFIFOx when the ADC TMLB is enabled.
- */
-/*\{*/
-#define ADC_SSFIFO_TMLB_CNT_M 0x000003C0 ///< Continuous Sample Counter
-#define ADC_SSFIFO_TMLB_CONT 0x00000020 ///< Continuation Sample Indicator
-#define ADC_SSFIFO_TMLB_DIFF 0x00000010 ///< Differential Sample Indicator
-#define ADC_SSFIFO_TMLB_TS 0x00000008 ///< Temp Sensor Sample Indicator
-#define ADC_SSFIFO_TMLB_MUX_M 0x00000007 ///< Analog Input Indicator
-#define ADC_SSFIFO_TMLB_CNT_S 6 ///< Sample counter shift
-#define ADC_SSFIFO_TMLB_MUX_S 0 ///< Input channel number shift
-/*\}*/
/**
* The following are defines for the bit fields in the COMP_O_ACMIS register.
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