Change filename and macros from AT91SAM3.. to SAM3.. to conform to Atmel's official...

[bertos.git] / bertos / cpu / cortex-m3 / io / sam3.h

diff --git a/bertos/cpu/cortex-m3/io/sam3.h b/bertos/cpu/cortex-m3/io/sam3.h
index c637d59e49a25fa15e8af00a20e0fe50ee824bdf..2b58220db3487621e8d826b5c476a668a6b4aa64 100644 (file)
--- a/bertos/cpu/cortex-m3/io/sam3.h
+++ b/bertos/cpu/cortex-m3/io/sam3.h
@@ -43,7 +43,7 @@
  * Peripherals IDs.
  */
 /*\{*/
-#if CPU_CM3_AT91SAM3N
+#if CPU_CM3_SAM3N
        #define SUPC_ID      0   ///< Supply Controller (SUPC)
        #define RSTC_ID      1   ///< Reset Controller (RSTC)
        #define RTC_ID       2   ///< Real Time Clock (RTC)
@@ -79,6 +79,24 @@
  * Hardware features for drivers.
  */
 #define USART_HAS_PDC  1
+#define SPI_HAS_PDC    1
+
+/* PDC registers */
+#define PERIPH_RPR_OFF  0x100  // Receive Pointer Register.
+#define PERIPH_RCR_OFF  0x104  // Receive Counter Register.
+#define PERIPH_TPR_OFF  0x108  // Transmit Pointer Register.
+#define PERIPH_TCR_OFF  0x10C  // Transmit Counter Register.
+#define PERIPH_RNPR_OFF 0x110  // Receive Next Pointer Register.
+#define PERIPH_RNCR_OFF 0x114  // Receive Next Counter Register.
+#define PERIPH_TNPR_OFF 0x118  // Transmit Next Pointer Register.
+#define PERIPH_TNCR_OFF 0x11C  // Transmit Next Counter Register.
+#define PERIPH_PTCR_OFF 0x120  // PDC Transfer Control Register.
+#define PERIPH_PTSR_OFF 0x124  // PDC Transfer Status Register.
+
+#define PDC_RXTEN  0
+#define PDC_RXTDIS 1
+#define PDC_TXTEN  8
+#define PDC_TXTDIS 9
 
 
 #include "sam3_sysctl.h"
@@ -96,7 +114,7 @@
  * UART I/O pins
  */
 /*\{*/
-#if CPU_CM3_AT91SAM3U
+#if CPU_CM3_SAM3U
        #define RXD0   11
        #define TXD0   12
 #else
@@ -111,7 +129,7 @@
  * PIO I/O pins
  */
 /*\{*/
-#if CPU_CM3_AT91SAM3U
+#if CPU_CM3_SAM3U
        #define SPI0_SPCK   15
        #define SPI0_MOSI   14
        #define SPI0_MISO   13