Manage the page writing on two banks. Move flash info in sam3 defines.

[bertos.git] / bertos / cpu / cortex-m3 / io / sam3.h

diff --git a/bertos/cpu/cortex-m3/io/sam3.h b/bertos/cpu/cortex-m3/io/sam3.h
index 24fefc007b81312d30fefdfba4585f8952063977..3d007d50b2a037ae8a20e5a36f8ae0a3fe0bfd17 100644 (file)
--- a/bertos/cpu/cortex-m3/io/sam3.h
+++ b/bertos/cpu/cortex-m3/io/sam3.h
@@ -140,6 +140,7 @@
 #include "sam3_sysctl.h"
 #include "sam3_pdc.h"
 #include "sam3_pmc.h"
+#include "sam3_dmac.h"
 #include "sam3_smc.h"
 #include "sam3_sdramc.h"
 #include "sam3_ints.h"
@@ -157,6 +158,8 @@
 #include "sam3_tc.h"
 #include "sam3_twi.h"
 #include "sam3_ssc.h"
+#include "sam3_hsmci.h"
+#include "sam3_chipid.h"
 
 /**
  * U(S)ART I/O pins
@@ -290,6 +293,7 @@
 
 #if CPU_CM3_SAM3X
        #define SSC_PORT            PIOA_BASE
+       #define SSC_PIO_PDR         PIOA_PDR
        #define SSC_RECV_PERIPH     PIO_PERIPH_A
        #define SSC_TRAN_PERIPH     PIO_PERIPH_B
        #define SSC_RD              18
@@ -298,9 +302,54 @@
        #define SSC_TD              16
        #define SSC_TF              15
        #define SSC_TK              14
+#elif CPU_CM3_SAM3N
+       #define SSC_PORT            /* None! */
+       #define SSC_PIO_PDR         /* None! */
+       #define SSC_RECV_PERIPH     /* None! */
+       #define SSC_TRAN_PERIPH     /* None! */
+       #define SSC_RD              /* None! */
+       #define SSC_RF              /* None! */
+       #define SSC_RK              /* None! */
+       #define SSC_TD              /* None! */
+       #define SSC_TF              /* None! */
+       #define SSC_TK              /* None! */
+#elif CPU_CM3_SAM3S
+       #define SSC_PORT            PIOA_BASE
+       #define SSC_PIO_PDR         PIOA_PDR
+       #define SSC_RECV_PERIPH     PIO_PERIPH_A
+       #define SSC_TRAN_PERIPH     PIO_PERIPH_A
+       #define SSC_RD              18
+       #define SSC_RF              20
+       #define SSC_RK              19
+       #define SSC_TD              17
+       #define SSC_TF              15
+       #define SSC_TK              16
+#elif CPU_CM3_SAM3U
+       #define SSC_PORT            PIOA_BASE
+       #define SSC_PIO_PDR         PIOA_PDR
+       #define SSC_RECV_PERIPH     PIO_PERIPH_A
+       #define SSC_TRAN_PERIPH     PIO_PERIPH_A
+       #define SSC_RD              27
+       #define SSC_RF              31
+       #define SSC_RK              29
+       #define SSC_TD              26
+       #define SSC_TF              30
+       #define SSC_TK              28
 #else
        #error no ssc pins are defined for this cpu
 #endif
 
+
+#if CPU_CM3_SAM3X8
+       #define FLASH_MEM_SIZE          0x80000UL ///< Internal flash memory size
+       #define FLASH_PAGE_SIZE_BYTES         256 ///< Size of cpu flash memory page in bytes
+       #define FLASH_BANKS_NUM                 2 ///< Number of flash banks
+       #define FLASH_PAGES_FOR_BANK         1024 ///< Number pages for each bank
+       #define FLASH_BASE                    0x0
+#else
+       #error no internal flash info are defined for this cpu
+#endif
+
+
 /*\}*/
 #endif /* SAM3_H */