Add ssc pins definition for sam3 family.

[bertos.git] / bertos / cpu / cortex-m3 / io / sam3.h

diff --git a/bertos/cpu/cortex-m3/io/sam3.h b/bertos/cpu/cortex-m3/io/sam3.h
index ef5efa05baf67ade81538c0c7c3676c755cef259..8b69cb4480fe2b878ab2875415d8cce2f239c925 100644 (file)
--- a/bertos/cpu/cortex-m3/io/sam3.h
+++ b/bertos/cpu/cortex-m3/io/sam3.h
@@ -137,27 +137,11 @@
        #error undefined U(S)ART_PORTS for this cpu
 #endif
 
-/* PDC registers */
-#define PERIPH_RPR_OFF  0x100  // Receive Pointer Register.
-#define PERIPH_RCR_OFF  0x104  // Receive Counter Register.
-#define PERIPH_TPR_OFF  0x108  // Transmit Pointer Register.
-#define PERIPH_TCR_OFF  0x10C  // Transmit Counter Register.
-#define PERIPH_RNPR_OFF 0x110  // Receive Next Pointer Register.
-#define PERIPH_RNCR_OFF 0x114  // Receive Next Counter Register.
-#define PERIPH_TNPR_OFF 0x118  // Transmit Next Pointer Register.
-#define PERIPH_TNCR_OFF 0x11C  // Transmit Next Counter Register.
-#define PERIPH_PTCR_OFF 0x120  // PDC Transfer Control Register.
-#define PERIPH_PTSR_OFF 0x124  // PDC Transfer Status Register.
-
-#define PDC_RXTEN  0
-#define PDC_RXTDIS 1
-#define PDC_TXTEN  8
-#define PDC_TXTDIS 9
-
-
 #include "sam3_sysctl.h"
+#include "sam3_pdc.h"
 #include "sam3_pmc.h"
 #include "sam3_smc.h"
+#include "sam3_sdramc.h"
 #include "sam3_ints.h"
 #include "sam3_pio.h"
 #include "sam3_nvic.h"
@@ -166,6 +150,13 @@
 #include "sam3_spi.h"
 #include "sam3_flash.h"
 #include "sam3_wdt.h"
+#include "sam3_emac.h"
+#include "sam3_rstc.h"
+#include "sam3_adc.h"
+#include "sam3_dacc.h"
+#include "sam3_tc.h"
+#include "sam3_twi.h"
+#include "sam3_ssc.h"
 
 /**
  * U(S)ART I/O pins
@@ -240,7 +231,7 @@
 /*\}*/
 
 /**
- * PIO I/O pins
+ * SPI I/O pins
  */
 /*\{*/
 #if CPU_CM3_SAM3U
@@ -256,5 +247,94 @@
        #define SPI0_MOSI   13
        #define SPI0_MISO   12
 #endif
+/*\}*/
+
+/**
+ * TWI I/O pins
+ */
+/*\{*/
+#if CPU_CM3_SAM3X
+       #define TWI0_PORT   PIOA_BASE
+       #define TWI1_PORT   PIOA_BASE
+
+       #define TWI0_PERIPH  PIO_PERIPH_A
+       #define TWI1_PERIPH  PIO_PERIPH_A
+
+       #define TWI0_TWD    17
+       #define TWI0_TWCK   18
+       #define TWI1_TWD    12
+       #define TWI1_TWCK   13
+#elif CPU_CM3_SAM3N || CPU_CM3_SAM3S
+       #define TWI0_PORT   PIOA_BASE
+       #define TWI1_PORT   PIOB_BASE
+
+       #define TWI0_PERIPH  PIO_PERIPH_A
+       #define TWI1_PERIPH  PIO_PERIPH_A
+
+       #define TWI0_TWD    3
+       #define TWI0_TWCK   4
+       #define TWI1_TWD    4
+       #define TWI1_TWCK   5
+#elif CPU_CM3_SAM3U
+       #define TWI0_PORT   PIOA_BASE
+       #define TWI1_PORT   PIOA_BASE
+
+       #define TWI0_PERIPH  PIO_PERIPH_A
+       #define TWI1_PERIPH  PIO_PERIPH_A
+
+       #define TWI0_TWD    9
+       #define TWI0_TWCK   10
+       #define TWI1_TWD    24
+       #define TWI1_TWCK   25
+#endif
+
+#if CPU_CM3_SAM3X
+       #define SSC_PORT            PIOA_BASE
+       #define SSC_PIO_PDR         PIOA_PDR
+       #define SSC_RECV_PERIPH     PIO_PERIPH_A
+       #define SSC_TRAN_PERIPH     PIO_PERIPH_B
+       #define SSC_RD              18
+       #define SSC_RF              17
+       #define SSC_RK              19
+       #define SSC_TD              16
+       #define SSC_TF              15
+       #define SSC_TK              14
+#elif CPU_CM3_SAM3N
+       #define SSC_PORT            /* None! */
+       #define SSC_PIO_PDR         /* None! */
+       #define SSC_RECV_PERIPH     /* None! */
+       #define SSC_TRAN_PERIPH     /* None! */
+       #define SSC_RD              /* None! */
+       #define SSC_RF              /* None! */
+       #define SSC_RK              /* None! */
+       #define SSC_TD              /* None! */
+       #define SSC_TF              /* None! */
+       #define SSC_TK              /* None! */
+#elif CPU_CM3_SAM3S
+       #define SSC_PORT            PIOA_BASE
+       #define SSC_PIO_PDR         PIOA_PDR
+       #define SSC_RECV_PERIPH     PIO_PERIPH_A
+       #define SSC_TRAN_PERIPH     PIO_PERIPH_A
+       #define SSC_RD              18
+       #define SSC_RF              20
+       #define SSC_RK              19
+       #define SSC_TD              17
+       #define SSC_TF              15
+       #define SSC_TK              16
+#elif CPU_CM3_SAM3U
+       #define SSC_PORT            PIOA_BASE
+       #define SSC_PIO_PDR         PIOA_PDR
+       #define SSC_RECV_PERIPH     PIO_PERIPH_A
+       #define SSC_TRAN_PERIPH     PIO_PERIPH_A
+       #define SSC_RD              27
+       #define SSC_RF              31
+       #define SSC_RK              29
+       #define SSC_TD              26
+       #define SSC_TF              30
+       #define SSC_TK              28
+#else
+       #error no ssc pins are defined for this cpu
+#endif
+
 /*\}*/
 #endif /* SAM3_H */