Remove duplicate define. Put all phy chip specific defines in its

[bertos.git] / bertos / cpu / cortex-m3 / io / sam3.h

diff --git a/bertos/cpu/cortex-m3/io/sam3.h b/bertos/cpu/cortex-m3/io/sam3.h
index 8fa50e6d6489b4cb2b3028114db0eec57031c9e3..bedb1ce68fae36385f6496dbf6a54dce735d60a6 100644 (file)
--- a/bertos/cpu/cortex-m3/io/sam3.h
+++ b/bertos/cpu/cortex-m3/io/sam3.h
@@ -346,10 +346,53 @@
        #define FLASH_BANKS_NUM                 2 ///< Number of flash banks
        #define FLASH_PAGES_FOR_BANK         1024 ///< Number pages for each bank
        #define FLASH_BASE                0x80000 ///< Start address for bank 0
+#elif CPU_CM3_SAM3U4
+       #define FLASH_MEM_SIZE          0x40000UL ///< Internal flash memory size
+       #define FLASH_PAGE_SIZE_BYTES         256 ///< Size of cpu flash memory page in bytes
+       #define FLASH_BANKS_NUM                 2 ///< Number of flash banks
+       #define FLASH_PAGES_FOR_BANK          512 ///< Number pages for each bank
+       #define FLASH_BASE                0x80000 ///< Start address for bank 0
+#elif CPU_CM3_SAM3N4 || CPU_CM3_SAM3S4
+       #define FLASH_MEM_SIZE          0x40000UL ///< Internal flash memory size
+       #define FLASH_PAGE_SIZE_BYTES         256 ///< Size of cpu flash memory page in bytes
+       #define FLASH_BANKS_NUM                 1 ///< Number of flash banks
+       #define FLASH_PAGES_FOR_BANK         1024 ///< Number pages for each bank
+       #define FLASH_BASE               0x400000 ///< Start address for bank 0
 #else
        #error no internal flash info are defined for this cpu
 #endif
 
 
-/*\}*/
+#if CPU_CM3_SAM3X8
+       // Port B
+       #define PHY_REFCLK_XT2_BIT      0
+       #define PHY_TXEN_BIT            1
+       #define PHY_TXD0_BIT            2
+       #define PHY_TXD1_BIT            3
+       #define PHY_RXDV_TESTMODE_BIT   4
+       #define PHY_RXD0_AD0_BIT        5
+       #define PHY_RXD1_AD1_BIT        6
+       #define PHY_RXER_RXD4_RPTR_BIT  7
+       #define PHY_MDC_BIT             8
+       #define PHY_MDIO_BIT            9
+       // Port A
+       #define PHY_MDINTR_BIT          5
+#elif (CPU_CM3_SAM3U || CPU_CM3_SAM3N)
+       /* No ethernet interface is present on this cpu */
+#else
+       #error No MII/RMII PHY pins interface was define for select CPU.
+#endif
+
+#define PHY_MII_PINS_PORTB \
+       BV(PHY_REFCLK_XT2_BIT) \
+       | BV(PHY_TXEN_BIT) \
+       | BV(PHY_TXD0_BIT) \
+       | BV(PHY_TXD1_BIT) \
+       | BV(PHY_RXD0_AD0_BIT) \
+       | BV(PHY_RXD1_AD1_BIT) \
+       | BV(PHY_RXER_RXD4_RPTR_BIT) \
+       | BV(PHY_MDC_BIT) \
+       | BV(PHY_MDIO_BIT)
+
+
 #endif /* SAM3_H */