Add Device ID Base Address register to the STM32 memory map.

[bertos.git] / bertos / cpu / cortex-m3 / io / sam3_adc.h

diff --git a/bertos/cpu/cortex-m3/io/sam3_adc.h b/bertos/cpu/cortex-m3/io/sam3_adc.h
index 47fcaed43c9b4bf485cc174b6fc896966e3c42d0..c855dc850d9bff03b97b006d27ce0b4c40874361 100644 (file)
--- a/bertos/cpu/cortex-m3/io/sam3_adc.h
+++ b/bertos/cpu/cortex-m3/io/sam3_adc.h
@@ -162,7 +162,7 @@
 #define ADC_SR          (*((reg32_t *)(ADC_BASE + ADC_SR_OFF))) ///< Status register address.
 
 
-#define ADC_CH_MASK              0x000000FF    ///< Channel mask.
+#define ADC_CH_MASK              0x0000FFFF    ///< Channel mask.
 #define ADC_CH0                           0    ///< Channel 0
 #define ADC_CH1                           1    ///< Channel 1
 #define ADC_CH2                           2    ///< Channel 2
@@ -248,6 +248,7 @@
 #define ADC_ACR_OFF              0x00000094     ///< Analog control register offeset.
 #define ADC_ACR          (*((reg32_t *)(ADC_BASE + ADC_ACR_OFF))) ///< Analog control register.
 #define ADC_TSON                          4     ///< Temperature Sensor On.
+#define ADC_TEMPERATURE_CH               15     ///< Channel where is the internal sensor temperature
 /* \} */
 
 #endif /* SAM3_ADC_H */