Update the tcp_server example to use the correct ip input callback.

[bertos.git] / bertos / cpu / cortex-m3 / io / sam3_dacc.h

diff --git a/bertos/cpu/cortex-m3/io/sam3_dacc.h b/bertos/cpu/cortex-m3/io/sam3_dacc.h
index 27fcc56e2dd4ce36921e02c31bec2d41de72c7b6..562d5f495f988ff486dc3e3edb6973bce0556930 100644 (file)
--- a/bertos/cpu/cortex-m3/io/sam3_dacc.h
+++ b/bertos/cpu/cortex-m3/io/sam3_dacc.h
@@ -49,7 +49,7 @@
  * \{
  */
 #define DACC_CR_OFF              0x00000000     ///< Control register offeset.
-#define DACC_CR          (*((reg32_t*) (DACC_BASE + DACC_CR_OFF)))    ///< Control register address.
+#define DACC_CR          (*((reg32_t*)(DACC_BASE + DACC_CR_OFF)))    ///< Control register address.
 #define DACC_SWRST                        0      ///< Software reset.
 /* \} */
 
@@ -74,6 +74,19 @@
 #define DACC_STARTUP_MASK        0x3F000000      ///< Startup time selection
 #define DACC_STARTUP_SHIFT               24      ///< Startup time selsection shift
 
+
+/**
+ * Trigger selection.
+ * $WIZ$ sam3x_dac_tc = "DACC_TRGSEL_TIO_CH0", "DACC_TRGSEL_TIO_CH1", "DACC_TRGSEL_TIO_CH2", "DACC_TRGSEL_PWM0", "DACC_TRGSEL_PWM1"
+ * \{
+ */
+ #define DACC_TRGSEL_TIO_CH0    1
+ #define DACC_TRGSEL_TIO_CH1    2
+ #define DACC_TRGSEL_TIO_CH2    3
+ #define DACC_TRGSEL_PWM0       4
+ #define DACC_TRGSEL_PWM1       5
+/* \} */
+
 #define DACC_MR_STARTUP_0                 0      ///< 0 periods of DACClock
 #define DACC_MR_STARTUP_8                 1      ///< 8 periods of DACClock
 #define DACC_MR_STARTUP_16                2      ///< 16 periods of of DACClock
@@ -152,8 +165,8 @@
 /**
  * DACC Interrupt disable register
  */
-#define DACC_IMR_OFF             0x0000002C     ///< Interrupt disable register offeset.
-#define DACC_IMR          (*((reg32_t*) (DACC_BASE + DACC_IMR_OFF)))    ///< Interrupt disable register address.
+#define DACC_IMR_OFF             0x0000002C     ///< Interrupt mask register offeset.
+#define DACC_IMR          (*((reg32_t*) (DACC_BASE + DACC_IMR_OFF)))    ///< Interrupt mask register address.
 
 /**
  * DACC Interrupt status register
@@ -163,7 +176,7 @@
 
 #define DACC_TXRDY                        0     ///< Transmit ready interrupt
 #define DACC_EOC                          1     ///< End of conversion interrupt
-#define DACC_ENDTX                        2     ///< End of transmit buffer interrupt
+#define DACC_ENDTX                        2     ///< End of DMA Interrupt Flag
 #define DACC_TXBUFE                       3     ///< Transmit buffer empty interrupt