Fix flash start address.

[bertos.git] / bertos / cpu / cortex-m3 / io / sam3_dacc.h

diff --git a/bertos/cpu/cortex-m3/io/sam3_dacc.h b/bertos/cpu/cortex-m3/io/sam3_dacc.h
index 7192a33de74a9be12e7ac6c34c6f4c3ede12028f..e2071dd72ed3654a4608bc71981413dfb62dd548 100644 (file)
--- a/bertos/cpu/cortex-m3/io/sam3_dacc.h
+++ b/bertos/cpu/cortex-m3/io/sam3_dacc.h
@@ -41,6 +41,8 @@
 #ifndef SAM3_DACC_H
 #define SAM3_DACC_H
 
+#include <io/cm3.h>
+
 /** DACC registers base. */
 #define DACC_BASE               0x400C8000
 
@@ -49,7 +51,7 @@
  * \{
  */
 #define DACC_CR_OFF              0x00000000     ///< Control register offeset.
-#define DACC_CR          (*((reg32_t*) (DACC_BASE + DACC_CR_OFF)))    ///< Control register address.
+#define DACC_CR          (*((reg32_t*)(DACC_BASE + DACC_CR_OFF)))    ///< Control register address.
 #define DACC_SWRST                        0      ///< Software reset.
 /* \} */
 
@@ -74,6 +76,19 @@
 #define DACC_STARTUP_MASK        0x3F000000      ///< Startup time selection
 #define DACC_STARTUP_SHIFT               24      ///< Startup time selsection shift
 
+
+/**
+ * Trigger selection.
+ * $WIZ$ sam3x_dac_tc = "DACC_TRGSEL_TIO_CH0", "DACC_TRGSEL_TIO_CH1", "DACC_TRGSEL_TIO_CH2", "DACC_TRGSEL_PWM0", "DACC_TRGSEL_PWM1"
+ * \{
+ */
+ #define DACC_TRGSEL_TIO_CH0    1
+ #define DACC_TRGSEL_TIO_CH1    2
+ #define DACC_TRGSEL_TIO_CH2    3
+ #define DACC_TRGSEL_PWM0       4
+ #define DACC_TRGSEL_PWM1       5
+/* \} */
+
 #define DACC_MR_STARTUP_0                 0      ///< 0 periods of DACClock
 #define DACC_MR_STARTUP_8                 1      ///< 8 periods of DACClock
 #define DACC_MR_STARTUP_16                2      ///< 16 periods of of DACClock
@@ -152,8 +167,8 @@
 /**
  * DACC Interrupt disable register
  */
-#define DACC_IMR_OFF             0x0000002C     ///< Interrupt disable register offeset.
-#define DACC_IMR          (*((reg32_t*) (DACC_BASE + DACC_IMR_OFF)))    ///< Interrupt disable register address.
+#define DACC_IMR_OFF             0x0000002C     ///< Interrupt mask register offeset.
+#define DACC_IMR          (*((reg32_t*) (DACC_BASE + DACC_IMR_OFF)))    ///< Interrupt mask register address.
 
 /**
  * DACC Interrupt status register
@@ -163,7 +178,7 @@
 
 #define DACC_TXRDY                        0     ///< Transmit ready interrupt
 #define DACC_EOC                          1     ///< End of conversion interrupt
-#define DACC_ENDTX                        2     ///< End of transmit buffer interrupt
+#define DACC_ENDTX                        2     ///< End of DMA Interrupt Flag
 #define DACC_TXBUFE                       3     ///< Transmit buffer empty interrupt
 
 
@@ -171,42 +186,23 @@
  * DMA controller for DACC
  * DACC PDC register.
  */
-#define DACC_RPR_OFF                     0x100 ///< Receive Pointer Register.
-#define DACC_RPR        (*((reg32_t*) (DACC_BASE + DACC_RPR_OFF)))    ///< Receive Pointer Register.
-\r
-#define DACC_RCR_OFF                     0x104 ///< Receive Counter Register.
-#define DACC_RCR       (*((reg32_t*) (DACC_BASE + DACC_RCR_OFF)))   ///<  Receive Counter Register.
-\r
-#define DACC_TPR_OFF                     0x108 ///< Transmit Pointer Register.
-#define DACC_TPR       (*((reg32_t*) (DACC_BASE + DACC_TPR_OFF)))   ///<  Transmit Pointer Register.
-\r
-#define DACC_TCR_OFF                     0x10C ///< Transmit Counter Register.
-#define DACC_TCR       (*((reg32_t*) (DACC_BASE + DACC_TCR_OFF)))   ///< Transmit Counter Register.
-\r
-#define DACC_RNPR_OFF                    0x110 ///< Receive Next Pointer Register.
-#define DACC_RNPR      (*((reg32_t*) (DACC_BASE + DACC_RNPR_OFF)))   ///< Receive Next Pointer Register.
-\r
-#define DACC_RNCR_OFF                    0x114 ///< Receive Next Counter Register.
-#define DACC_RNCR      (*((reg32_t*) (DACC_BASE + DACC_RNCR_OFF)))   ///< Receive Next Counter Register.
-\r
-#define DACC_TNPR_OFF                    0x118 ///< Transmit Next Pointer Register.
-#define DACC_TNPR      (*((reg32_t*) (DACC_BASE + DACC_TNPR_OFF)))   ///< Transmit Next Pointer Register.
-\r
-#define DACC_TNCR_OFF                    0x11C ///< Transmit Next Counter Register.
-#define DACC_TNCR      (*((reg32_t*) (DACC_BASE + DACC_TNCR_OFF)))   ///< Transmit Next Counter Register.
-\r
-#define DACC_PTCR_OFF                    0x120 ///< Transfer Control Register.
-#define DACC_PTCR      (*((reg32_t*) (DACC_BASE + DACC_PTCR_OFF)))  ///< Transfer Control Register.
-\r
-#define DACC_PTSR_OFF                    0x124 ///< Transfer Status Register.
-#define DACC_PTSR      (*((reg32_t*) (DACC_BASE + DACC_PTSR_OFF)))    ///< Transfer Status Register.
-
-
-#define DACC_PTCR_RXTEN               0  ///< DACC_PTCR  Receiver Transfer Enable.\r
-#define DACC_PTCR_RXTDIS              1  ///< DACC_PTCR  Receiver Transfer Disable.\r
-#define DACC_PTCR_TXTEN               8  ///< DACC_PTCR  Transmitter Transfer Enable.\r
-#define DACC_PTCR_TXTDIS              9  ///< DACC_PTCR  Transmitter Transfer Disable.\r
-#define DACC_PTSR_RXTEN               0  ///< DACC_PTSR  Receiver Transfer Enable.\r
+#define DACC_RPR       (*((reg32_t*) (DACC_BASE + PERIPH_RPR_OFF)))  ///< Receive Pointer Register.
+#define DACC_RCR       (*((reg32_t*) (DACC_BASE + PERIPH_RCR_OFF)))  ///<  Receive Counter Register.
+#define DACC_TPR       (*((reg32_t*) (DACC_BASE + PERIPH_TPR_OFF)))  ///<  Transmit Pointer Register.
+#define DACC_TCR       (*((reg32_t*) (DACC_BASE + PERIPH_TCR_OFF)))  ///< Transmit Counter Register.
+#define DACC_RNPR      (*((reg32_t*) (DACC_BASE + PERIPH_RNPR_OFF))) ///< Receive Next Pointer Register.
+#define DACC_RNCR      (*((reg32_t*) (DACC_BASE + PERIPH_RNCR_OFF))) ///< Receive Next Counter Register.
+#define DACC_TNPR      (*((reg32_t*) (DACC_BASE + PERIPH_TNPR_OFF))) ///< Transmit Next Pointer Register.
+#define DACC_TNCR      (*((reg32_t*) (DACC_BASE + PERIPH_TNCR_OFF))) ///< Transmit Next Counter Register.
+#define DACC_PTCR      (*((reg32_t*) (DACC_BASE + PERIPH_PTCR_OFF))) ///< Transfer Control Register.
+#define DACC_PTSR      (*((reg32_t*) (DACC_BASE + PERIPH_PTSR_OFF))) ///< Transfer Status Register.
+
+
+#define DACC_PTCR_RXTEN               0  ///< DACC_PTCR  Receiver Transfer Enable.
+#define DACC_PTCR_RXTDIS              1  ///< DACC_PTCR  Receiver Transfer Disable.
+#define DACC_PTCR_TXTEN               8  ///< DACC_PTCR  Transmitter Transfer Enable.
+#define DACC_PTCR_TXTDIS              9  ///< DACC_PTCR  Transmitter Transfer Disable.
+#define DACC_PTSR_RXTEN               0  ///< DACC_PTSR  Receiver Transfer Enable.
 #define DACC_PTSR_TXTEN               8  ///< DACC_PTSR  Transmitter Transfer Enable.
 
 #endif /* SAM3_DACC_H */