Fix typos.

[bertos.git] / bertos / cpu / cortex-m3 / io / sam3_pmc.h

diff --git a/bertos/cpu/cortex-m3/io/sam3_pmc.h b/bertos/cpu/cortex-m3/io/sam3_pmc.h
index 4664838d0e33e86d90f9fac80831083b7454b5b6..3d561a883680777825bcf08ef45c37c9ef6d2a9f 100644 (file)
--- a/bertos/cpu/cortex-m3/io/sam3_pmc.h
+++ b/bertos/cpu/cortex-m3/io/sam3_pmc.h
@@ -36,34 +36,6 @@
 #ifndef SAM3_PMC_H
 #define SAM3_PMC_H
 
-// FIXME: move these in sam3(?)_int.h
-#define INT_SUPC     0  ///< SAM3N Supply Controller (SUPC)
-#define INT_RSTC     1  ///< SAM3N Reset Controller (RSTC)
-#define INT_RTC      2  ///< SAM3N Real Time Clock (RTC)
-#define INT_RTT      3  ///< SAM3N Real Time Timer (RTT)
-#define INT_WDT      4  ///< SAM3N Watchdog Timer (WDT)
-#define INT_PMC      5  ///< SAM3N Power Management Controller (PMC)
-#define INT_EFC      6  ///< SAM3N Enhanced Flash Controller (EFC)
-#define INT_UART0    8  ///< SAM3N UART 0 (UART0)
-#define INT_UART1    9  ///< SAM3N UART 1 (UART1)
-#define INT_PIOA    11  ///< SAM3N Parallel I/O Controller A (PIOA)
-#define INT_PIOB    12  ///< SAM3N Parallel I/O Controller B (PIOB)
-#define INT_PIOC    13  ///< SAM3N Parallel I/O Controller C (PIOC)
-#define INT_USART0  14  ///< SAM3N USART 0 (USART0)
-#define INT_USART1  15  ///< SAM3N USART 1 (USART1)
-#define INT_TWI0    19  ///< SAM3N Two Wire Interface 0 (TWI0)
-#define INT_TWI1    20  ///< SAM3N Two Wire Interface 1 (TWI1)
-#define INT_SPI     21  ///< SAM3N Serial Peripheral Interface (SPI)
-#define INT_TC0     23  ///< SAM3N Timer/Counter 0 (TC0)
-#define INT_TC1     24  ///< SAM3N Timer/Counter 1 (TC1)
-#define INT_TC2     25  ///< SAM3N Timer/Counter 2 (TC2)
-#define INT_TC3     26  ///< SAM3N Timer/Counter 3 (TC3)
-#define INT_TC4     27  ///< SAM3N Timer/Counter 4 (TC4)
-#define INT_TC5     28  ///< SAM3N Timer/Counter 5 (TC5)
-#define INT_ADC     29  ///< SAM3N Analog To Digital Converter (ADC)
-#define INT_DACC    30  ///< SAM3N Digital To Analog Converter (DACC)
-#define INT_PWM     31  ///< SAM3N Pulse Width Modulation (PWM)
-
 /**
  * PMC registers.
  */
@@ -74,9 +46,9 @@
 #define PMC_PCER_R  (*((reg32_t *)0x400E0410))   ///< Peripheral Clock Enable Register
 #define PMC_PCDR_R  (*((reg32_t *)0x400E0414))   ///< Peripheral Clock Disable Register
 #define PMC_PCSR_R  (*((reg32_t *)0x400E0418))   ///< Peripheral Clock Status Register
-#define PMC_MOR_R   (*((reg32_t *)0x400E0420))   ///< Main Oscillator Register
-#define PMC_MCFR_R  (*((reg32_t *)0x400E0424))   ///< Main Clock Frequency Register
-#define PMC_PLLR_R  (*((reg32_t *)0x400E0428))   ///< PLL Register
+#define CKGR_MOR_R  (*((reg32_t *)0x400E0420))   ///< Main Oscillator Register
+#define CKGR_MCFR_R (*((reg32_t *)0x400E0424))   ///< Main Clock Frequency Register
+#define CKGR_PLLR_R (*((reg32_t *)0x400E0428))   ///< PLL Register
 #define PMC_MCKR_R  (*((reg32_t *)0x400E0430))   ///< Master Clock Register
 #define PMC_PCK_R   (*((reg32_t *)0x400E0440))   ///< Programmable Clock 0 Register
 #define PMC_IER_R   (*((reg32_t *)0x400E0460))   ///< Interrupt Enable Register
@@ -290,13 +262,13 @@
  */
 /*\{*/
 #define CKGR_PLLR_DIV_M           0xff   ///< Divider mask
-#define CKGR_PLLR_DIV(value)      ((CKGR_PLLR_DIV_M & (value))
+#define CKGR_PLLR_DIV(value)      (CKGR_PLLR_DIV_M & (value))
 #define CKGR_PLLR_PLLCOUNT_S      8
 #define CKGR_PLLR_PLLCOUNT_M      (0x3f << CKGR_PLLR_PLLCOUNT_S)   ///< PLL Counter mask
-#define CKGR_PLLR_PLLCOUNT(value) ((CKGR_PLLR_PLLCOUNT_M & ((value) << CKGR_PLLR_PLLCOUNT_S)))
+#define CKGR_PLLR_PLLCOUNT(value) (CKGR_PLLR_PLLCOUNT_M & ((value) << CKGR_PLLR_PLLCOUNT_S))
 #define CKGR_PLLR_MUL_S           16
 #define CKGR_PLLR_MUL_M           (0x7ff << CKGR_PLLR_MUL_S)   ///< PLL Multiplier mask
-#define CKGR_PLLR_MUL(value)      ((CKGR_PLLR_MUL_M & ((value) << CKGR_PLLR_MUL_S)))
+#define CKGR_PLLR_MUL(value)      (CKGR_PLLR_MUL_M & ((value) << CKGR_PLLR_MUL_S))
 #define CKGR_PLLR_STUCKTO1        BV(29)
 /*\}*/