sam3 smc definitions, add ECC registers.

[bertos.git] / bertos / cpu / cortex-m3 / io / sam3_smc.h

diff --git a/bertos/cpu/cortex-m3/io/sam3_smc.h b/bertos/cpu/cortex-m3/io/sam3_smc.h
index 81e20e8e6b0c576d64e451798b188b4bd08729d6..7dc977e0bcc7d3132c7d68de3263b0e7254a634a 100644 (file)
--- a/bertos/cpu/cortex-m3/io/sam3_smc.h
+++ b/bertos/cpu/cortex-m3/io/sam3_smc.h
@@ -240,6 +240,43 @@
 /*\}*/
 
 
+/**
+ * Defines for bit fields in SMC_CFG register.
+ */
+/*\{*/
+#define SMC_CFG_PAGESIZE_SHIFT       0
+#define SMC_CFG_PAGESIZE_MASK        (0x3 << SMC_CFG_PAGESIZE_SHIFT)
+#define SMC_CFG_PAGESIZE_PS512_16    (0x0 << 0)
+#define SMC_CFG_PAGESIZE_PS1024_32   (0x1 << 0)
+#define SMC_CFG_PAGESIZE_PS2048_64   (0x2 << 0)
+#define SMC_CFG_PAGESIZE_PS4096_128  (0x3 << 0)
+#define SMC_CFG_WSPARE               (0x1 << 8)
+#define SMC_CFG_RSPARE               (0x1 << 9)
+#define SMC_CFG_EDGECTRL             (0x1 << 12)
+#define SMC_CFG_RBEDGE               (0x1 << 13)
+#define SMC_CFG_DTOCYC_SHIFT         16
+#define SMC_CFG_DTOCYC_MASK          (0xf << SMC_CFG_DTOCYC_SHIFT)
+#define SMC_CFG_DTOCYC(value)        (SMC_CFG_DTOCYC_MASK & ((value) << SMC_CFG_DTOCYC_SHIFT))
+#define SMC_CFG_DTOMUL_SHIFT         20
+#define SMC_CFG_DTOMUL_MASK          (0x7 << SMC_CFG_DTOMUL_SHIFT)
+#define SMC_CFG_DTOMUL_X1            (0x0 << 20)
+#define SMC_CFG_DTOMUL_X16           (0x1 << 20)
+#define SMC_CFG_DTOMUL_X128          (0x2 << 20)
+#define SMC_CFG_DTOMUL_X256          (0x3 << 20)
+#define SMC_CFG_DTOMUL_X1024         (0x4 << 20)
+#define SMC_CFG_DTOMUL_X4096         (0x5 << 20)
+#define SMC_CFG_DTOMUL_X65536        (0x6 << 20)
+#define SMC_CFG_DTOMUL_X1048576      (0x7 << 20)
+/*\}*/
+
+/**
+ * Defines for bit fields in SMC_CTRL register.
+ */
+/*\{*/
+#define SMC_CTRL_NFCEN   BV(0)
+#define SMC_CTRL_NFCDIS  BV(1)
+/*\}*/
+
 /**
  * Defines for bit fields in SMC_SR register.
  */
@@ -260,6 +297,31 @@
 #define SMC_SR_RB_EDGE0      BV(24)
 /*\}*/
 
+/**
+ * Defines for bit fields in SMC_ECC_CTRL register
+ */
+/*\{*/
+#define SMC_ECC_CTRL_RST    BV(0)
+#define SMC_ECC_CTRL_SWRST  BV(1)
+/*\}*/
+
+/**
+ * Defines for bit fields in SMC_ECC_MD register
+ */
+/*\{*/
+#define SMC_ECC_MD_ECC_PAGESIZE_SHIFT        0
+#define SMC_ECC_MD_ECC_PAGESIZE_MASK         0x3
+#define SMC_ECC_MD_ECC_PAGESIZE_PS512_16     0x0
+#define SMC_ECC_MD_ECC_PAGESIZE_PS1024_32    0x1
+#define SMC_ECC_MD_ECC_PAGESIZE_PS2048_64    0x2
+#define SMC_ECC_MD_ECC_PAGESIZE_PS4096_128   0x3
+#define SMC_ECC_MD_TYPCORREC_SHIFT           4
+#define SMC_ECC_MD_TYPCORREC_MASK            (0x3 << SMC_ECC_MD_TYPCORREC_SHIFT)
+#define SMC_ECC_MD_TYPCORREC_CPAGE           (0x0 << SMC_ECC_MD_TYPCORREC_SHIFT)
+#define SMC_ECC_MD_TYPCORREC_C256B           (0x1 << SMC_ECC_MD_TYPCORREC_SHIFT)
+#define SMC_ECC_MD_TYPCORREC_C512B           (0x2 << SMC_ECC_MD_TYPCORREC_SHIFT)
+/*\}*/
+
 /**
  * Defines for bit fields in SMC_SETUP registers.
  */