Move the pdc definition in separate file and comply the other headers.

[bertos.git] / bertos / cpu / cortex-m3 / io / sam3_smc.h

diff --git a/bertos/cpu/cortex-m3/io/sam3_smc.h b/bertos/cpu/cortex-m3/io/sam3_smc.h
index ab915f4f1d0f0dd92d967fb926c070b93d01f9f3..8998d8364e2801a5376d6f9b25cbed3f4777d912 100644 (file)
--- a/bertos/cpu/cortex-m3/io/sam3_smc.h
+++ b/bertos/cpu/cortex-m3/io/sam3_smc.h
@@ -203,6 +203,119 @@
 #define SMC_WPSR       (*((reg32_t *)(SMC_BASE + SMC_WPSR_OFF)))
 /*\}*/
 
+/**
+ * NFC control addresses.
+ */
+/*\{*/
+#define NFC_SRAM_BASE_ADDR  0x20100000  ///< Base address of NFC SRAM
+#define NFC_CMD_BASE_ADDR   0x60000000  ///< Base address for NFC Address Command
+/*\}*/
+
+/**
+ * NFC address command values.
+ */
+/*\{*/
+#define NFC_CMD_CMD1           (0xFF <<  2)  ///< Command Register Value for Cycle 1
+#define NFC_CMD_CMD2           (0xFF << 10)  ///< Command Register Value for Cycle 2
+#define NFC_CMD_VCMD2          BV(18)        ///< Valid Cycle 2 Command
+#define NFC_CMD_ACYCLE_SHIFT   19
+#define NFC_CMD_ACYCLE_MASK    (0x7 << 19)   ///< Number of Address required for the current command
+#define NFC_CMD_ACYCLE_NONE    (0x0 << 19)   ///< No address cycle
+#define NFC_CMD_ACYCLE_ONE     (0x1 << 19)   ///< One address cycle
+#define NFC_CMD_ACYCLE_TWO     (0x2 << 19)   ///< Two address cycles
+#define NFC_CMD_ACYCLE_THREE   (0x3 << 19)   ///< Three address cycles
+#define NFC_CMD_ACYCLE_FOUR    (0x4 << 19)   ///< Four address cycles
+#define NFC_CMD_ACYCLE_FIVE    (0x5 << 19)   ///< Five address cycles
+#define NFC_CMD_CSID_SHIFT     22            ///< Chip Select shift
+#define NFC_CMD_CSID_MASK      (0x7 << NFC_CMD_CSID_SHIFT)   ///< Chip Select mask
+#define NFC_CMD_NFCEN          BV(25)        ///< NFC Enable
+#define NFC_CMD_NFCWR          BV(26)        ///< NFC Write Enable
+#define NFC_CMD_NFCCMD         BV(27)        ///< NFC Command Enable
+/*\}*/
+
+
+/**
+ * Defines for bit fields in SMC_CFG register.
+ */
+/*\{*/
+#define SMC_CFG_PAGESIZE_SHIFT       0
+#define SMC_CFG_PAGESIZE_MASK        (0x3 << SMC_CFG_PAGESIZE_SHIFT)
+#define SMC_CFG_PAGESIZE_PS512_16    (0x0 << 0)
+#define SMC_CFG_PAGESIZE_PS1024_32   (0x1 << 0)
+#define SMC_CFG_PAGESIZE_PS2048_64   (0x2 << 0)
+#define SMC_CFG_PAGESIZE_PS4096_128  (0x3 << 0)
+#define SMC_CFG_WSPARE               (0x1 << 8)
+#define SMC_CFG_RSPARE               (0x1 << 9)
+#define SMC_CFG_EDGECTRL             (0x1 << 12)
+#define SMC_CFG_RBEDGE               (0x1 << 13)
+#define SMC_CFG_DTOCYC_SHIFT         16
+#define SMC_CFG_DTOCYC_MASK          (0xf << SMC_CFG_DTOCYC_SHIFT)
+#define SMC_CFG_DTOCYC(value)        (SMC_CFG_DTOCYC_MASK & ((value) << SMC_CFG_DTOCYC_SHIFT))
+#define SMC_CFG_DTOMUL_SHIFT         20
+#define SMC_CFG_DTOMUL_MASK          (0x7 << SMC_CFG_DTOMUL_SHIFT)
+#define SMC_CFG_DTOMUL_X1            (0x0 << 20)
+#define SMC_CFG_DTOMUL_X16           (0x1 << 20)
+#define SMC_CFG_DTOMUL_X128          (0x2 << 20)
+#define SMC_CFG_DTOMUL_X256          (0x3 << 20)
+#define SMC_CFG_DTOMUL_X1024         (0x4 << 20)
+#define SMC_CFG_DTOMUL_X4096         (0x5 << 20)
+#define SMC_CFG_DTOMUL_X65536        (0x6 << 20)
+#define SMC_CFG_DTOMUL_X1048576      (0x7 << 20)
+/*\}*/
+
+/**
+ * Defines for bit fields in SMC_CTRL register.
+ */
+/*\{*/
+#define SMC_CTRL_NFCEN   BV(0)
+#define SMC_CTRL_NFCDIS  BV(1)
+/*\}*/
+
+/**
+ * Defines for bit fields in SMC_SR register.
+ */
+/*\{*/
+#define SMC_SR_SMCSTS        BV(0)
+#define SMC_SR_RB_RISE       BV(4)
+#define SMC_SR_RB_FALL       BV(5)
+#define SMC_SR_NFCBUSY       BV(8)
+#define SMC_SR_NFCWR         BV(11)
+#define SMC_SR_NFCSID_SHIFT  12
+#define SMC_SR_NFCSID_MASK   (0x7 << SMC_SR_NFCSID_SHIFT)
+#define SMC_SR_XFRDONE       BV(16)
+#define SMC_SR_CMDDONE       BV(17)
+#define SMC_SR_DTOE          BV(20)
+#define SMC_SR_UNDEF         BV(21)
+#define SMC_SR_AWB           BV(22)
+#define SMC_SR_NFCASE        BV(23)
+#define SMC_SR_RB_EDGE0      BV(24)
+/*\}*/
+
+/**
+ * Defines for bit fields in SMC_ECC_CTRL register
+ */
+/*\{*/
+#define SMC_ECC_CTRL_RST    BV(0)
+#define SMC_ECC_CTRL_SWRST  BV(1)
+/*\}*/
+
+/**
+ * Defines for bit fields in SMC_ECC_MD register
+ */
+/*\{*/
+#define SMC_ECC_MD_ECC_PAGESIZE_SHIFT        0
+#define SMC_ECC_MD_ECC_PAGESIZE_MASK         0x3
+#define SMC_ECC_MD_ECC_PAGESIZE_PS512_16     0x0
+#define SMC_ECC_MD_ECC_PAGESIZE_PS1024_32    0x1
+#define SMC_ECC_MD_ECC_PAGESIZE_PS2048_64    0x2
+#define SMC_ECC_MD_ECC_PAGESIZE_PS4096_128   0x3
+#define SMC_ECC_MD_TYPCORREC_SHIFT           4
+#define SMC_ECC_MD_TYPCORREC_MASK            (0x3 << SMC_ECC_MD_TYPCORREC_SHIFT)
+#define SMC_ECC_MD_TYPCORREC_CPAGE           (0x0 << SMC_ECC_MD_TYPCORREC_SHIFT)
+#define SMC_ECC_MD_TYPCORREC_C256B           (0x1 << SMC_ECC_MD_TYPCORREC_SHIFT)
+#define SMC_ECC_MD_TYPCORREC_C512B           (0x2 << SMC_ECC_MD_TYPCORREC_SHIFT)
+/*\}*/
+
 /**
  * Defines for bit fields in SMC_SETUP registers.
  */