Add some missign register defines. Reformat.

[bertos.git] / bertos / cpu / cortex-m3 / io / sam3_tc.h

diff --git a/bertos/cpu/cortex-m3/io/sam3_tc.h b/bertos/cpu/cortex-m3/io/sam3_tc.h
index a918f6c82e5d8c9b5b8b9d3898d0d12586fb32eb..dfd5a56d83ec69e75240de3f2d27390a56c47349 100644 (file)
--- a/bertos/cpu/cortex-m3/io/sam3_tc.h
+++ b/bertos/cpu/cortex-m3/io/sam3_tc.h
@@ -71,6 +71,7 @@
 #define TC_CCR_SWTRG                 2 ///< Software Trigger Command
 
 #define TC_TIMER_CLOCK1              0 ///< Select timer clock TCLK1
+#define TC_TIMER_CLOCK2              1 ///< Select timer clock TCLK2
 
 #define TC0_SMMR0_OFF             0x08  ///< TC0 Stepper Motor Mode Register (channel = 0).
 #define TC0_SMMR0             (*((reg32_t*)(TC0_BASE + TC0_SMMR0_OFF)))  ///< TC0 Stepper Motor Mode Register (channel = 0).