/**
* USART base addresses.
*/
-#if CPU_CM3_SAM3U
+#if CPU_CM3_SAM3N
+ #define USART0_BASE 0x40024000
+ #define USART1_BASE 0x40028000
+#elif CPU_CM3_SAM3U
#define USART0_BASE 0x40090000
#define USART1_BASE 0x40094000
#define USART2_BASE 0x40098000
#define USART3_BASE 0x4009C000
-#else
- #define USART0_BASE 0x40024000
- #define USART1_BASE 0x40028000
+#elif CPU_CM3_SAM3X
+ #define USART0_BASE 0x40098000
+ #define USART1_BASE 0x4009C000
+ #define USART2_BASE 0x400A0000
+ #define USART3_BASE 0x400A4000
#endif
/**