Fix sample time adc settings. Calibrate ADC when we init it.

[bertos.git] / bertos / cpu / cortex-m3 / io / stm32_adc.h

diff --git a/bertos/cpu/cortex-m3/io/stm32_adc.h b/bertos/cpu/cortex-m3/io/stm32_adc.h
index b884b5265630fce6c8e5f467455f21a58c226f62..c34f3127ff1152fe3cbd8faf124952c2a7039eef 100644 (file)
--- a/bertos/cpu/cortex-m3/io/stm32_adc.h
+++ b/bertos/cpu/cortex-m3/io/stm32_adc.h
@@ -81,8 +81,8 @@
 #define ADC_CHANNEL_13                              ((uint8_t)0x0D)
 #define ADC_CHANNEL_14                              ((uint8_t)0x0E)
 #define ADC_CHANNEL_15                              ((uint8_t)0x0F)
-#define ADC_CHANNEL_16                              ((uint8_t)0X10)
-#define ADC_CHANNEL_17                              ((uint8_t)0X11)
+#define ADC_CHANNEL_16                              ((uint8_t)0x10)
+#define ADC_CHANNEL_17                              ((uint8_t)0x11)
 
 /* ADC sampling times */
 #define ADC_SAMPLETIME_1CYCLES5                    ((uint8_t)0x00)
@@ -247,6 +247,27 @@
 #define SR_JEOC                                        2
 #define SR_JSTRT                                       3
 #define SR_STRT                                        4
+
+/* ADC sample time */
+#define SMPR1_CH17                                    21
+#define SMPR1_CH16                                    18
+#define SMPR1_CH15                                    15
+#define SMPR1_CH14                                    12
+#define SMPR1_CH13                                     9
+#define SMPR1_CH12                                     6
+#define SMPR1_CH11                                     3
+#define SMPR1_CH10                                     0
+
+#define SMPR2_CH9                                     27
+#define SMPR2_CH8                                     24
+#define SMPR2_CH7                                     21
+#define SMPR2_CH6                                     18
+#define SMPR2_CH5                                     15
+#define SMPR2_CH4                                     12
+#define SMPR2_CH3                                      9
+#define SMPR2_CH2                                      6
+#define SMPR2_CH1                                      3
+#define SMPR2_CH0                                      0
 \r
 /* ADC registers Masks */\r
 #define CR1_ADC_CLEAR_MASK             ((uint32_t)0xFFF0FEFF)\r