#define ADC_FLAG_STRT ((uint8_t)0X10)
-/* ADC ADON mask */\r
-#define CR2_ADON_SET ((uint32_t)0x00000001)\r
-#define CR2_ADON_RESET ((uint32_t)0xFFFFFFFE)\r
-\r
-/* ADC DMA mask */\r
-#define CR2_DMA_SET ((uint16_t)0x0100)\r
-#define CR2_DMA_RESET ((uint16_t)0xFEFF)\r
-\r
-/* ADC RSTCAL mask */\r
-#define CR2_RSTCAL_SET ((uint16_t)0x0008)\r
-\r
-/* ADC CAL mask */\r
-#define CR2_CAL_SET ((uint16_t)0x0004)\r
-\r
-/* ADC SWSTRT mask */\r
-#define CR2_SWSTRT_SET ((uint32_t)0x00400000)\r
-\r
-/* ADC DISCNUM mask */\r
-#define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF)\r
-\r
-/* ADC DISCEN mask */\r
-#define CR1_DISCEN_SET ((uint32_t)0x00000800)\r
-#define CR1_DISCEN_RESET ((uint32_t)0xFFFFF7FF)\r
-\r
-/* ADC EXTTRIG mask */\r
-#define CR2_EXTTRIG_SET ((uint32_t)0x00100000)\r
-#define CR2_EXTTRIG_RESET ((uint32_t)0xFFEFFFFF)\r
-\r
-/* ADC Software start mask */\r
-#define CR2_EXTTRIG_SWSTRT_SET ((uint32_t)0x00500000)\r
-#define CR2_EXTTRIG_SWSTRT_RESET ((uint32_t)0xFFAFFFFF)\r
-\r
-/* ADC JAUTO mask */\r
-#define CR1_JAUTO_SET ((uint32_t)0x00000400)\r
-#define CR1_JAUTO_RESET ((uint32_t)0xFFFFFBFF)\r
-\r
-/* ADC JDISCEN mask */\r
-#define CR1_JDISCEN_SET ((uint32_t)0x00001000)\r
-#define CR1_JDISCEN_RESET ((uint32_t)0xFFFFEFFF)\r
-\r
-/* ADC JEXTSEL mask */\r
-#define CR2_JEXTSEL_RESET ((uint32_t)0xFFFF8FFF)\r
-\r
-/* ADC JEXTTRIG mask */\r
-#define CR2_JEXTTRIG_SET ((uint32_t)0x00008000)\r
-#define CR2_JEXTTRIG_RESET ((uint32_t)0xFFFF7FFF)\r
-\r
-/* ADC JSWSTRT mask */\r
-#define CR2_JSWSTRT_SET ((uint32_t)0x00200000)\r
-\r
-/* ADC injected software start mask */\r
-#define CR2_JEXTTRIG_JSWSTRT_SET ((uint32_t)0x00208000)\r
-#define CR2_JEXTTRIG_JSWSTRT_RESET ((uint32_t)0xFFDF7FFF)\r
-\r
-/* ADC AWDCH mask */\r
-#define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0)\r
-\r
-/* ADC SQx mask */\r
-#define SQR3_SQ_MASK ((uint8_t)0x1F)\r
-#define SQR2_SQ_MASK ((uint8_t)0x1F)\r
+/* ADC ADON mask */
+#define CR2_ADON_SET ((uint32_t)0x00000001)
+#define CR2_ADON_RESET ((uint32_t)0xFFFFFFFE)
+
+/* ADC DMA mask */
+#define CR2_DMA_SET ((uint16_t)0x0100)
+#define CR2_DMA_RESET ((uint16_t)0xFEFF)
+
+/* ADC RSTCAL mask */
+#define CR2_RSTCAL_SET ((uint16_t)0x0008)
+
+/* ADC CAL mask */
+#define CR2_CAL_SET ((uint16_t)0x0004)
+
+/* ADC SWSTRT mask */
+#define CR2_SWSTRT_SET ((uint32_t)0x00400000)
+
+/* ADC DISCNUM mask */
+#define CR1_DISCNUM_RESET ((uint32_t)0xFFFF1FFF)
+
+/* ADC DISCEN mask */
+#define CR1_DISCEN_SET ((uint32_t)0x00000800)
+#define CR1_DISCEN_RESET ((uint32_t)0xFFFFF7FF)
+
+/* ADC EXTTRIG mask */
+#define CR2_EXTTRIG_SET ((uint32_t)0x00100000)
+#define CR2_EXTTRIG_RESET ((uint32_t)0xFFEFFFFF)
+
+/* ADC Software start mask */
+#define CR2_EXTTRIG_SWSTRT_SET ((uint32_t)0x00500000)
+#define CR2_EXTTRIG_SWSTRT_RESET ((uint32_t)0xFFAFFFFF)
+
+/* ADC JAUTO mask */
+#define CR1_JAUTO_SET ((uint32_t)0x00000400)
+#define CR1_JAUTO_RESET ((uint32_t)0xFFFFFBFF)
+
+/* ADC JDISCEN mask */
+#define CR1_JDISCEN_SET ((uint32_t)0x00001000)
+#define CR1_JDISCEN_RESET ((uint32_t)0xFFFFEFFF)
+
+/* ADC JEXTSEL mask */
+#define CR2_JEXTSEL_RESET ((uint32_t)0xFFFF8FFF)
+
+/* ADC JEXTTRIG mask */
+#define CR2_JEXTTRIG_SET ((uint32_t)0x00008000)
+#define CR2_JEXTTRIG_RESET ((uint32_t)0xFFFF7FFF)
+
+/* ADC JSWSTRT mask */
+#define CR2_JSWSTRT_SET ((uint32_t)0x00200000)
+
+/* ADC injected software start mask */
+#define CR2_JEXTTRIG_JSWSTRT_SET ((uint32_t)0x00208000)
+#define CR2_JEXTTRIG_JSWSTRT_RESET ((uint32_t)0xFFDF7FFF)
+
+/* ADC AWDCH mask */
+#define CR1_AWDCH_RESET ((uint32_t)0xFFFFFFE0)
+
+/* ADC SQx mask */
+#define SQR3_SQ_MASK ((uint8_t)0x1F)
+#define SQR2_SQ_MASK ((uint8_t)0x1F)
#define SQR1_SQ_MASK ((uint8_t)0x1F)
#define SQR1_SQ_LEN_MASK 0xF
-#define SQR1_SQ_LEN_SHIFT 20\r
-\r
-/* ADC JSQx mask */\r
-#define JSQR_JSQ_SET ((uint8_t)0x1F)\r
-\r
-/* ADC JL mask */\r
-#define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF)\r
-\r
-/* ADC SMPx mask */\r
-#define SMPR1_SMP_SET ((uint8_t)0x07)\r
-#define SMPR2_SMP_SET ((uint8_t)0x07)\r
-\r
-/* ADC Analog watchdog enable mode mask */\r
-#define CR1_AWDMODE_RESET ((uint32_t)0xFF3FFDFF)\r
-\r
-/* ADC TSPD mask */\r
-#define CR2_TSVREFE_SET ((uint32_t)0x00800000)\r
-#define CR2_TSVREFE_RESET ((uint32_t)0xFF7FFFFF)\r
-\r
-/* ADC JDRx registers= offset */\r
-#define JDR_OFFSET ((uint8_t)0x28)\r
+#define SQR1_SQ_LEN_SHIFT 20
+
+/* ADC JSQx mask */
+#define JSQR_JSQ_SET ((uint8_t)0x1F)
+
+/* ADC JL mask */
+#define JSQR_JL_RESET ((uint32_t)0xFFCFFFFF)
+
+/* ADC SMPx mask */
+#define SMPR1_SMP_SET ((uint8_t)0x07)
+#define SMPR2_SMP_SET ((uint8_t)0x07)
+
+/* ADC Analog watchdog enable mode mask */
+#define CR1_AWDMODE_RESET ((uint32_t)0xFF3FFDFF)
+
+/* ADC TSPD mask */
+#define CR2_TSVREFE_SET ((uint32_t)0x00800000)
+#define CR2_TSVREFE_RESET ((uint32_t)0xFF7FFFFF)
+
+/* ADC JDRx registers= offset */
+#define JDR_OFFSET ((uint8_t)0x28)
/* ADC CR1 register */
#define CR1_EOCIE 5
#define SMPR2_CH2 6
#define SMPR2_CH1 3
#define SMPR2_CH0 0
-\r
-/* ADC registers Masks */\r
-#define CR1_ADC_CLEAR_MASK ((uint32_t)0xFFF0FEFF)\r
-#define CR2_ADC_CLEAR_MASK ((uint32_t)0xFFF1F7FD)\r
+
+/* ADC registers Masks */
+#define CR1_ADC_CLEAR_MASK ((uint32_t)0xFFF0FEFF)
+#define CR2_ADC_CLEAR_MASK ((uint32_t)0xFFF1F7FD)
#define SQR1_CLEAR_MASK ((uint32_t)0xFF0FFFFF)
/* ADC defines for SMT32F103Bxx */
-#define ADC_TEMP_V25 4.3
-#define ADC_TEMP_SLOPE 1.43
-#define ADC_TEMP_CONST 25
-#define ADC_TEMP_CH 16
-#define ADC_VREFINT_CH 17
-\r
+#define ADC_TEMP_V25 4300 // uV / C
+#define ADC_TEMP_SLOPE 1430 // mV
+#define ADC_TEMP_CONST 25000
+#define ADC_TEMP_CH 16
+#define ADC_VREFINT_CH 17
+
struct stm32_adc
{
reg32_t SR;
projects / bertos.git / blobdiff