Add embedded flash module for stm32. First refactor of emb flash using kblock.

[bertos.git] / bertos / cpu / cortex-m3 / io / stm32_memmap.h

diff --git a/bertos/cpu/cortex-m3/io/stm32_memmap.h b/bertos/cpu/cortex-m3/io/stm32_memmap.h
index a99577a174b05db215ecef9e26c91143b05c5100..b8317caf4584f72e10c6bc98406fd36465a0b409 100644 (file)
--- a/bertos/cpu/cortex-m3/io/stm32_memmap.h
+++ b/bertos/cpu/cortex-m3/io/stm32_memmap.h
@@ -57,17 +57,26 @@
 #define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
 #define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
 #define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
 #define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
 #define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
 #define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
 #define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
 #define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
 #define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)
 #define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
 #define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
-#define CAN_BASE              (APB1PERIPH_BASE + 0x6400)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
+#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800)
 #define BKP_BASE              (APB1PERIPH_BASE + 0x6C00)
 #define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
+#define CEC_BASE              (APB1PERIPH_BASE + 0x7800)
 
 #define AFIO_BASE             (APB2PERIPH_BASE + 0x0000)
 #define EXTI_BASE             (APB2PERIPH_BASE + 0x0400)
@@ -76,21 +85,54 @@
 #define GPIOC_BASE            (APB2PERIPH_BASE + 0x1000)
 #define GPIOD_BASE            (APB2PERIPH_BASE + 0x1400)
 #define GPIOE_BASE            (APB2PERIPH_BASE + 0x1800)
+#define GPIOF_BASE            (APB2PERIPH_BASE + 0x1C00)
+#define GPIOG_BASE            (APB2PERIPH_BASE + 0x2000)
 #define ADC1_BASE             (APB2PERIPH_BASE + 0x2400)
 #define ADC2_BASE             (APB2PERIPH_BASE + 0x2800)
 #define TIM1_BASE             (APB2PERIPH_BASE + 0x2C00)
 #define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
+#define TIM8_BASE             (APB2PERIPH_BASE + 0x3400)
 #define USART1_BASE           (APB2PERIPH_BASE + 0x3800)
+#define ADC3_BASE             (APB2PERIPH_BASE + 0x3C00)
+#define TIM15_BASE            (APB2PERIPH_BASE + 0x4000)
+#define TIM16_BASE            (APB2PERIPH_BASE + 0x4400)
+#define TIM17_BASE            (APB2PERIPH_BASE + 0x4800)
 
-#define DMA_BASE              (AHBPERIPH_BASE + 0x0000)
-#define DMA_CHANNEL1_BASE     (AHBPERIPH_BASE + 0x0008)
-#define DMA_CHANNEL2_BASE     (AHBPERIPH_BASE + 0x001C)
-#define DMA_CHANNEL3_BASE     (AHBPERIPH_BASE + 0x0030)
-#define DMA_CHANNEL4_BASE     (AHBPERIPH_BASE + 0x0044)
-#define DMA_CHANNEL5_BASE     (AHBPERIPH_BASE + 0x0058)
-#define DMA_CHANNEL6_BASE     (AHBPERIPH_BASE + 0x006C)
-#define DMA_CHANNEL7_BASE     (AHBPERIPH_BASE + 0x0080)
-#define RCC_BASE              (AHBPERIPH_BASE + 0x1000)
+#define SDIO_BASE             (PERIPH_BASE + 0x18000)
+
+
+#define DMA1_BASE             (AHBPERIPH_BASE + 0X0000)
+#define DMA1_CHANNEL1_BASE    (AHBPERIPH_BASE + 0X0008)
+#define DMA1_CHANNEL2_BASE    (AHBPERIPH_BASE + 0X001C)
+#define DMA1_CHANNEL3_BASE    (AHBPERIPH_BASE + 0X0030)
+#define DMA1_CHANNEL4_BASE    (AHBPERIPH_BASE + 0X0044)
+#define DMA1_CHANNEL5_BASE    (AHBPERIPH_BASE + 0X0058)
+#define DMA1_CHANNEL6_BASE    (AHBPERIPH_BASE + 0X006C)
+#define DMA1_CHANNEL7_BASE    (AHBPERIPH_BASE + 0X0080)
+#define DMA2_BASE             (AHBPERIPH_BASE + 0X0400)
+#define DMA2_CHANNEL1_BASE    (AHBPERIPH_BASE + 0X0408)
+#define DMA2_CHANNEL2_BASE    (AHBPERIPH_BASE + 0X041C)
+#define DMA2_CHANNEL3_BASE    (AHBPERIPH_BASE + 0X0430)
+#define DMA2_CHANNEL4_BASE    (AHBPERIPH_BASE + 0X0444)
+#define DMA2_CHANNEL5_BASE    (AHBPERIPH_BASE + 0X0458)
+#define RCC_BASE              (AHBPERIPH_BASE + 0X1000)
+#define CRC_BASE              (AHBPERIPH_BASE + 0X3000)
+
+#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x2000) ///< Flash registers base address
+
+#define ETH_BASE              (AHBPERIPH_BASE + 0x8000)
+#define ETH_MAC_BASE          (ETH_BASE)
+#define ETH_MMC_BASE          (ETH_BASE + 0x0100)
+#define ETH_PTP_BASE          (ETH_BASE + 0x0700)
+#define ETH_DMA_BASE          (ETH_BASE + 0x1000)
+
+#define FSMC_BANK1_R_BASE     (FSMC_R_BASE + 0x0000) ///< FSMC Bank1 registers base address
+#define FSMC_BANK1E_R_BASE    (FSMC_R_BASE + 0x0104) ///< FSMC Bank1E registers base address
+#define FSMC_BANK2_R_BASE     (FSMC_R_BASE + 0x0060) ///< FSMC Bank2 registers base address
+#define FSMC_BANK3_R_BASE     (FSMC_R_BASE + 0x0080) ///< FSMC Bank3 registers base address
+#define FSMC_BANK4_R_BASE     (FSMC_R_BASE + 0x00A0) ///< FSMC Bank4 registers base address
+
+#define DBGMCU_BASE          ((uint32_t)0xE0042000) ///< Debug MCU registers base address
 
 /* System Control Space memory map */
 #define SCS_BASE              (0xE000E000)