Trailing whitespace

[bertos.git] / bertos / cpu / cortex-m3 / scripts / lm3s1968_ram.ld

diff --git a/bertos/cpu/cortex-m3/scripts/lm3s1968_ram.ld b/bertos/cpu/cortex-m3/scripts/lm3s1968_ram.ld
index 2bd20d96aac15fa6e072f0e6e9bb7b9933c3690b..2585d53a69400a95d4166edb45acd300171f79a8 100644 (file)
--- a/bertos/cpu/cortex-m3/scripts/lm3s1968_ram.ld
+++ b/bertos/cpu/cortex-m3/scripts/lm3s1968_ram.ld
@@ -36,108 +36,20 @@
  *
  */
 
-
-SEARCH_DIR(.)
-OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-
-/*
- * Define memory configuration for LM3S1968 board
- */
-MEMORY
-{
-  rom(rx) : org = 0x00000000, len = 256k
-  ram(rwx) : org = 0x20000000, len = 64k
-}
-
-
 /*
  * Define stack size here
+ * Variable used in the cortex-m3_ram.ld file
  */
-FIQ_STACK_SIZE = 0x0100;
-IRQ_STACK_SIZE = 0x0100;
-ABT_STACK_SIZE = 0x0100;
-UND_STACK_SIZE = 0x0100;
-SVC_STACK_SIZE = 0x0400;
+STACK_SIZE = 0x1000;
 
 /*
- * Allocate section memory
+ * Define memory configuration for LM3S1968 board
  */
-SECTIONS
+MEMORY
 {
-       .text :
-       {
-               KEEP(*(.vectors));
-               . = ALIGN (4);
-               KEEP(*(.init));
-               . = ALIGN (4);
-               *(.rodata .rodata.*);
-               . = ALIGN (4);
-               *(.text .text.*);
-               . = ALIGN (4);
-               *(.glue_7t);
-               . = ALIGN(4);
-               *(.glue_7);
-               . = ALIGN(4);
-       } > ram
-
-       _etext = .;
-       PROVIDE (__etext = .);
-
-       .data : AT (_etext)
-       {
-               PROVIDE (__data_start = .);
-               *(vtable)
-               . = ALIGN (0x400);
-               *(.data .data.*)
-               . = ALIGN (4);
-               _edata = .;
-               PROVIDE (__data_end = .);
-       } > ram
-
-       .bss :
-       {
-               PROVIDE (__bss_start = .);
-               *(.bss .bss.*)
-               . = ALIGN(4);
-               *(COMMON)
-               . = ALIGN(4);
-               PROVIDE (__bss_end = .);
-       } > ram
-
-       /*
-        * Allocated stack at the end of bss section.
-        * Data heap is allocate at end of stack.
-        */
-       PROVIDE (__stack_start = .);
-
-       PROVIDE (__stack_fiq_start = .);
-       . += FIQ_STACK_SIZE;
-       . = ALIGN(4);
-       PROVIDE (__stack_fiq_end = .);
-
-       PROVIDE (__stack_irq_start = .);
-       . += IRQ_STACK_SIZE;
-       . = ALIGN(4);
-       PROVIDE (__stack_irq_end = .);
-
-       PROVIDE (__stack_abt_start = .);
-       . += ABT_STACK_SIZE;
-       . = ALIGN(4);
-       PROVIDE (__stack_abt_end = .);
-
-       PROVIDE (__stack_und_start = .);
-       . += UND_STACK_SIZE;
-       . = ALIGN(4);
-       PROVIDE (__stack_und_end = .);
-
-       PROVIDE (__stack_svc_start = .);
-       . += SVC_STACK_SIZE;
-       . = ALIGN(4);
-       PROVIDE (__stack_svc_end = .);
-
-       PROVIDE (__stack_end = .);
-
-       PROVIDE (__heap_start = .);
+        rom(rx) : org = 0x00000000, len = 256k
+        ram(rwx) : org = 0x20000000, len = 64k
 }
 
+INCLUDE "bertos/cpu/cortex-m3/scripts/cortex-m3_ram.ld"
+