-
+/**
+ * \file
+ * <!--
+ * This file is part of BeRTOS.
+ *
+ * Bertos is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * As a special exception, you may use this file as part of a free software
+ * library without restriction. Specifically, if other files instantiate
+ * templates or use macros or inline functions from this file, or you compile
+ * this file and link it with other files to produce an executable, this
+ * file does not by itself cause the resulting executable to be covered by
+ * the GNU General Public License. This exception does not however
+ * invalidate any other reasons why the executable file might be covered by
+ * the GNU General Public License.
+ *
+ * Copyright 2009 Develer S.r.l. (http://www.develer.com/)
+ * -->
+ *
+ * \brief I2S driver implementation.
+ *
+ * \version $Id$
+ * \author Luca Ottaviano <lottaviano@develer.com>
+ */
#include "i2s.h"
#include <drv/timer.h>
-#include <cfg/macros.h>
#include <cfg/log.h>
#include <io/arm.h>
+#define DATALEN (15 & SSC_DATLEN_MASK)
+// FIXME: this is not correct for 16 <= DATALEN < 24
+#define PDC_DIV ((DATALEN / 8) + 1)
+/* PDC_DIV must be 1, 2 or 4, which are the bytes that are transferred
+ * each time the PDC reads from memory.
+ */
+STATIC_ASSERT(PDC_DIV % 2 == 0);
+#define PDC_COUNT (CONFIG_PLAY_BUF_LEN / PDC_DIV)
+
static uint8_t play_buf1[CONFIG_PLAY_BUF_LEN];
static uint8_t play_buf2[CONFIG_PLAY_BUF_LEN];
-/* |x|x|CONT|SECOND|FIRST|IS_PLAYING|CUR_BUF| */
-/* |7|6| 5 | 4 | 3 | 2 | 1 0 | */
-static uint8_t status;
-#define CURRENT_BUF 0x03
-#define IS_PLAYING 2
-#define FIRST_BUF_FULL 3
-#define SECOND_BUF_FULL 4
-#define CONTINUE_PLAY 5
-
-INLINE bool is_buffer_full(int bv)
-{
- return status & BV(bv);
-}
+// the buffer in PDC next is play_buf2
+volatile bool is_second_buf_next;
uint8_t *i2s_getBuffer(unsigned buf_num)
{
- kprintf("getBuffer start\n");
- if (status & BV(IS_PLAYING))
- return 0;
+ LOG_INFO("getBuffer start\n");
- if ((buf_num == I2S_FIRST_BUF) && !is_buffer_full(FIRST_BUF_FULL))
+ if (i2s_isPlaying())
{
- status |= BV(FIRST_BUF_FULL);
- kprintf("status [0x%02X]\n", status);
- return play_buf1;
+ ASSERT(0);
+ return 0;
}
- else if ((buf_num == I2S_SECOND_BUF) && !is_buffer_full(SECOND_BUF_FULL))
- {
- status |= BV(SECOND_BUF_FULL);
- kprintf("status [0x%02X]\n", status);
+
+ if (buf_num == I2S_SECOND_BUF)
return play_buf2;
- }
+ else if (buf_num == I2S_FIRST_BUF)
+ return play_buf1;
else
return 0;
}
uint8_t *i2s_getFreeBuffer(void)
{
- if (!(status & BV(IS_PLAYING)))
+ if (!i2s_isPlaying())
+ {
+ ASSERT(0);
return 0;
+ }
- // disable irq
- // ...
- // set continue flag
- // ...
- // set buf_full flag
- // ...
- // enable irq
- // ...
- // return the buffer
-
- if ((status & CURRENT_BUF) == I2S_FIRST_BUF && !is_buffer_full(SECOND_BUF_FULL))
- return play_buf2;
- else if ((status & CURRENT_BUF) == I2S_SECOND_BUF && !is_buffer_full(FIRST_BUF_FULL))
- return play_buf1;
- else
+ // wait PDC transmission end
+ if (!(SSC_SR & BV(SSC_ENDTX)))
return 0;
-}
-INLINE void setCurrentBuffer(int buffer)
-{
- status &= ~CURRENT_BUF;
- status |= CURRENT_BUF & buffer;
-}
+ uint8_t *ret_buf = 0;
+ // the last time we got called, the second buffer was in PDC next
+ if (is_second_buf_next)
+ {
+ is_second_buf_next = false;
+ ret_buf = play_buf1;
+ }
+ // the last time the first buffer was in PDC next
+ else
+ {
+ is_second_buf_next = true;
+ ret_buf = play_buf2;
+ }
-// code irq callback
-static void i2s_dma_tx_irq_handler(void) __attribute__ ((interrupt));
-static void i2s_dma_tx_irq_handler(void)
-{
- /*
- if (status & BV(CONTINUE_PLAY))
+ if (ret_buf)
{
- kprintf("irq\n");
- if ((status & CURRENT_BUF) == I2S_FIRST_BUF)
- {
- SSC_PTCR = BV(PDC_TXTDIS);
- SSC_TPR = (reg32_t)play_buf2;
- SSC_TCR = CONFIG_PLAY_BUF_LEN;
- SSC_PTCR = BV(PDC_TXTEN);
-
- setCurrentBuffer(I2S_SECOND_BUF);
- status &= ~BV(FIRST_BUF_FULL);
- status &= ~BV(CONTINUE_PLAY);
- }
- // TODO: refactor.
- else
- {
- SSC_PTCR = BV(PDC_TXTDIS);
- SSC_TPR = (reg32_t)play_buf1;
- SSC_TCR = CONFIG_PLAY_BUF_LEN;
- SSC_PTCR = BV(PDC_TXTEN);
-
- setCurrentBuffer(I2S_FIRST_BUF);
- status &= ~BV(SECOND_BUF_FULL);
- status &= ~BV(CONTINUE_PLAY);
- }
+ SSC_TNPR = (reg32_t) ret_buf;
+ SSC_TNCR = PDC_COUNT;
}
- */
- AIC_EOICR = 0;
+ return ret_buf;
}
bool i2s_start(void)
{
+ /* Some time must pass between disabling and enabling again the transmission
+ * on SSC. A good empirical value seems >15 us. We try to avoid putting an
+ * explicit delay, instead we disable the transmitter when a sound finishes
+ * and hope that the delay has passed before we enter here again.
+ */
SSC_CR = BV(SSC_TXDIS);
- //kprintf("%08lX\n", SSC_TCMR);
- timer_udelay(15);
+ timer_delay(10);
+
SSC_PTCR = BV(PDC_TXTDIS);
SSC_TPR = (reg32_t)play_buf1;
- SSC_TCR = CONFIG_PLAY_BUF_LEN / 2;
+ SSC_TCR = PDC_COUNT;
+ SSC_TNPR = (reg32_t)play_buf2;
+ SSC_TNCR = PDC_COUNT;
+ is_second_buf_next = true;
+
SSC_PTCR = BV(PDC_TXTEN);
+
/* enable output */
SSC_CR = BV(SSC_TXEN);
-// ASSERT(SSC_PTSR & BV(PDC_TXTEN));
- /*
- kprintf("i2s_start start\n");
- if (status & (BV(FIRST_BUF_FULL) | BV(SECOND_BUF_FULL)))
- {
- setCurrentBuffer(I2S_FIRST_BUF);
- SSC_PTCR = BV(PDC_TXTDIS);
- SSC_TPR = (reg32_t)play_buf1;
- SSC_TCR = CONFIG_PLAY_BUF_LEN;
-
- status |= BV(IS_PLAYING);
- status |= BV(CONTINUE_PLAY);
- kprintf("start: status [0x%02X]\n", status);
- SSC_PTCR = BV(PDC_TXTEN);
-
- return true;
- }
- else
- {
- kprintf("start: buffers are not full\n");
- return false;
- }
- */
return true;
}
-// TODO renderlo configurabile
-#define MCK_DIV 16
-#define DELAY ((1 << SSC_STTDLY_SHIFT) & SSC_STTDLY_MASK)
-#define PERIOD ((15 << (SSC_PERIOD_SHIFT)) & SSC_PERIOD_MASK)
-#define DATALEN (15 & SSC_DATLEN_MASK)
-#define DATNB ((1 << SSC_DATNB_SHIFT) & SSC_DATNB_MASK)
-#define FSLEN ((15 << SSC_FSLEN_SHIFT) & SSC_FSLEN_MASK)
+#define CONFIG_SAMPLE_FREQ 44100
+#define BITS_PER_CHANNEL 16
+#define N_OF_CHANNEL 2
+// TODO: check the computed value?
+/* The last parameter (2) is due to the hadware on at91sam7s. */
+#define MCK_DIV (CPU_FREQ / CONFIG_SAMPLE_FREQ / BITS_PER_CHANNEL / N_OF_CHANNEL / 2)
+
+#define CONFIG_DELAY 1
+#define CONFIG_PERIOD 15
+#define CONFIG_DATNB 1
+#define CONFIG_FSLEN 15
+
+#define DELAY ((CONFIG_DELAY << SSC_STTDLY_SHIFT) & SSC_STTDLY_MASK)
+#define PERIOD ((CONFIG_PERIOD << (SSC_PERIOD_SHIFT)) & SSC_PERIOD_MASK)
+#define DATNB ((CONFIG_DATNB << SSC_DATNB_SHIFT) & SSC_DATNB_MASK)
+#define FSLEN ((CONFIG_FSLEN << SSC_FSLEN_SHIFT) & SSC_FSLEN_MASK)
#define SSC_DMA_IRQ_PRIORITY 5
void i2s_init(void)
{
- //TODO sistemare i pin
- PIOA_PDR = BV(SPI1_SPCK) | BV(SPI1_MOSI) | BV(SPI1_NPCS0);
+ PIOA_PDR = BV(SSC_TK) | BV(SSC_TF) | BV(SSC_TD);
/* reset device */
SSC_CR = BV(SSC_SWRST);
/* Disable all irqs */
SSC_IDR = 0xFFFFFFFF;
- /* Set the vector. */
- AIC_SVR(SSC_ID) = i2s_dma_tx_irq_handler;
- /* Initialize to edge triggered with defined priority. */
- AIC_SMR(SPI0_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SSC_DMA_IRQ_PRIORITY;
+
/* Enable the SSC IRQ */
- AIC_IDCR = BV(SSC_ID);
- /* Enable interrupt on tx buffer empty */
- SSC_IER = BV(SSC_ENDTX);
+ AIC_IECR = BV(SSC_ID);
/* enable i2s */
PMC_PCER = BV(SSC_ID);
- /* set current buffer to 1 */
- status = 0x01;
- for (int i = 0; i < CONFIG_PLAY_BUF_LEN; ++i)
- {
- //uint32_t tmp = 0x5555;
- //uint32_t tmp2 = 0x9999;
- play_buf1[i] = i;
- //play_buf1[i+4] = tmp2;
- }
+ /* Enable SSC */
+ SSC_CR = BV(SSC_TXEN);
}
-
-
projects / bertos.git / blobdiff