* invalidate any other reasons why the executable file might be covered by
* the GNU General Public License.
*
- * Copyright 2003, 2004, 2006, 2008 Develer S.r.l. (http://www.develer.com/)
+ * Copyright 2003, 2004, 2006, 2008, 2009 Develer S.r.l. (http://www.develer.com/)
* Copyright 2000 Bernie Innocenti <bernie@codewiz.org>
* All Rights Reserved.
* -->
* \version $Id$
*
* \author Andrea Grandi <andrea@develer.com>
+ * \author Daniele Basile <asterix@develer.com>
*/
#ifndef HW_SIPO_H
#warning TODO:This is an example implementation, you must implement it!
-#define LOAD_HIGH /* Implement me! */
-#define LOAD_LOW /* Implement me! */
-#define LOAD_INIT /* Implement me! */
-#define SET_SCK_OUT /* Implement me! */
-#define SET_SOUT_OUT /* Implement me! */
-#define CLOCK_HIGH /* Implement me! */
-#define CLOCK_LOW /* Implement me! */
-#define SET_SOUT_HIGH /* Implement me! */
-#define SET_SOUT_LOW /* Implement me! */
-#define CLOCK_PULSE /* Implement me! */
-#define OE_OUT
-#define OE_LOW
+/**
+ * Mapping sipo connection on board.
+ * See scheme to more info.
+ */
+typedef enum SipoMap {
+
+ /* Add device here */
+
+ SIPO_CNT
+} SipoMap;
+
+
+/**
+ * Define the macros needed to set the serial input bit of SIPO device
+ * low or high.
+ */
+#define SIPO_SI_HIGH() do { /* Implement me! */ } while (0)
+#define SIPO_SI_LOW() do { /* Implement me! */ } while (0)
+
+/**
+ * Drive pin to load the bit, presented in serial-in pin,
+ * into sipo shift register.
+ */
+#define SIPO_SI_CLOCK(clk_pol)
+ do { \
+ /* Implement me! */ \
+ (void)clk_pol; \
+ } while (0)
+
+/**
+ * Clock the content of shift register to output.
+ */
+#define SIPO_LOAD(device, load_pol) \
+ do { \
+ /* Implement me! */ \
+ (void)device; \
+ (void)load_pol; \
+ } while (0)
+/**
+ * Enable the shift register output.
+ */
+#define SIPO_ENABLE() /* Implement me! */
+
+/**
+ * Set logic level for load signal
+ */
+#define SIPO_SET_LD_LEVEL(device, load_pol) \
+ do { \
+ /* Implement me! */ \
+ (void)device; \
+ (void)load_pol; \
+ } while (0)
+
+
+/**
+ * Sel logic level for clock signal
+ */
+#define SIPO_SET_CLK_LEVEL(clock_pol) \
+ do { \
+ /* Implement me! */ \
+ (void)clock_pol; \
+ } while (0)
+
+
+/**
+ * Do everything needed in order to init the SIPO pins.
+ */
+#define SIPO_INIT_PIN() \
+ do { \
+ /* Implement me! */ \
+ } while(0)
#endif /* HW_SIPO_H */