Fix minor typos

[bertos.git] / cfg / cpu.h

diff --git a/cfg/cpu.h b/cfg/cpu.h
old mode 100755 (executable)
new mode 100644 (file)
index 23d0ddf..8a94572
--- a/cfg/cpu.h
+++ b/cfg/cpu.h
@@ -1,9 +1,34 @@
 /**
  * \file
  * <!--
+ * This file is part of BeRTOS.
+ *
+ * Bertos is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ *
+ * As a special exception, you may use this file as part of a free software
+ * library without restriction.  Specifically, if other files instantiate
+ * templates or use macros or inline functions from this file, or you compile
+ * this file and link it with other files to produce an executable, this
+ * file does not by itself cause the resulting executable to be covered by
+ * the GNU General Public License.  This exception does not however
+ * invalidate any other reasons why the executable file might be covered by
+ * the GNU General Public License.
+ *
  * Copyright 2004, 2005 Develer S.r.l. (http://www.develer.com/)
  * Copyright 2004 Giovanni Bajo
- * This file is part of DevLib - See README.devlib for information.
+ *
  * -->
  *
  * \brief CPU-specific definitions
@@ -94,8 +119,8 @@
        #define CPU_REG_BITS           32
        #define CPU_REGS_CNT           16
        #define CPU_SAVED_REGS_CNT     FIXME
-       #define CPU_STACK_GROWS_UPWARD 0  //FIXME
-       #define CPU_SP_ON_EMPTY_SLOT   0  //FIXME
+       #define CPU_STACK_GROWS_UPWARD 0
+       #define CPU_SP_ON_EMPTY_SLOT   0
        #define CPU_BYTE_ORDER         (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
        #define CPU_HARVARD            0
 
@@ -135,6 +160,7 @@
        #else /* !__IAR_SYSTEMS_ICC__ */
 
                #warning "IRQ_ macros need testing!"
+               #warning "Test now or die :-)"
 
                #define NOP         asm volatile ("mov r0,r0" ::)
 
@@ -142,9 +168,9 @@
                do { \
                        asm volatile ( \
                                "mrs r0, cpsr\n\t" \
-                               "orr r0, r0, #0xb0\n\t" \
-                               "msr cpsr, r0" \
-                               :: \
+                               "orr r0, r0, #0xc0\n\t" \
+                               "msr cpsr_c, r0" \
+                               ::: "r0" \
                        ); \
                } while (0)
 
@@ -152,19 +178,18 @@
                do { \
                        asm volatile ( \
                                "mrs r0, cpsr\n\t" \
-                               "bic r0, r0, #0xb0\n\t" \
-                               "msr cpsr, r0" \
-                               :: \
+                               "bic r0, r0, #0xc0\n\t" \
+                               "msr cpsr_c, r0" \
+                               ::: "r0" \
                        ); \
                } while (0)
 
                #define IRQ_SAVE_DISABLE(x) \
                do { \
                        asm volatile ( \
-                               "mrs r0, cpsr\n\t" \
-                               "mov %0, r0\n\t" \
-                               "orr r0, r0, #0xb0\n\t" \
-                               "msr cpsr, r0" \
+                               "mrs %0, cpsr\n\t" \
+                               "orr r0, %0, #0xc0\n\t" \
+                               "msr cpsr_c, r0" \
                                : "=r" (x) \
                                : /* no inputs */ \
                                : "r0" \
@@ -174,11 +199,9 @@
                #define IRQ_RESTORE(x) \
                do { \
                        asm volatile ( \
-                               "mov r0, %0\n\t" \
-                               "msr cpsr, r0" \
+                               "msr cpsr_c, %0" \
                                : /* no outputs */ \
                                : "r" (x) \
-                               : "r0" \
                        ); \
                } while (0)
 
@@ -186,16 +209,14 @@
                ({ \
                        uint32_t sreg; \
                        asm volatile ( \
-                               "mrs r0, cpsr\n\t" \
-                               "mov %0, r0" \
+                               "mrs %0, cpsr\n\t" \
                                : "=r" (sreg) \
                                : /* no inputs */ \
-                               : "r0" \
                        ); \
-                       (bool)(sreg & 0xb0); \
+                       !((sreg & 0xc0) == 0xc0); \
                })
 
-       #endif /* __IAR_SYSTEMS_ICC_ */
+       #endif /* !__IAR_SYSTEMS_ICC_ */
 
 #elif CPU_PPC
        #define NOP                 asm volatile ("nop" ::)