/*#*
*#* $Log$
+ *#* Revision 1.10 2006/02/24 01:17:30 bernie
+ *#* CPU_SAVED_REGS_CNT: Declare for x86/x86_64.
+ *#*
+ *#* Revision 1.9 2006/02/23 09:08:43 bernie
+ *#* Add note for a frequently reported non-bug.
+ *#*
+ *#* Revision 1.8 2006/02/10 12:37:45 bernie
+ *#* Add support for ARM on IAR.
+ *#*
+ *#* Revision 1.7 2005/11/27 03:04:38 bernie
+ *#* Add POSIX emulation for IRQ_* macros; Add Qt support.
+ *#*
+ *#* Revision 1.6 2005/07/19 07:26:49 bernie
+ *#* Add missing #endif.
+ *#*
+ *#* Revision 1.5 2005/06/27 21:24:17 bernie
+ *#* CPU_CSOURCE(): New macro.
+ *#*
+ *#* Revision 1.4 2005/06/14 06:15:10 bernie
+ *#* Add X86_64 support.
+ *#*
+ *#* Revision 1.3 2005/04/12 04:06:17 bernie
+ *#* Catch missing CPU earlier.
+ *#*
*#* Revision 1.2 2005/04/11 19:10:27 bernie
*#* Include top-level headers from cfg/ subdir.
*#*
* \{
*/
#define CPU_BIG_ENDIAN 0x1234
-#define CPU_LITTLE_ENDIAN 0x3412
+#define CPU_LITTLE_ENDIAN 0x3412 /* Look twice, pal. This is not a bug. */
/*\}*/
/*! Macro to include cpu-specific versions of the headers. */
#define CPU_HEADER(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).h)
+/*! Macro to include cpu-specific versions of implementation files. */
+#define CPU_CSOURCE(module) PP_STRINGIZE(PP_CAT3(module, _, CPU_ID).c)
+
#if CPU_I196
#elif CPU_X86
#define NOP asm volatile ("nop")
- #define IRQ_DISABLE /* nothing */
- #define IRQ_ENABLE /* nothing */
- #define IRQ_SAVE_DISABLE(x) /* nothing */
- #define IRQ_RESTORE(x) /* nothing */
- typedef uint32_t cpuflags_t; // FIXME
- typedef uint32_t cpustack_t;
+ /* Get IRQ_* definitions from the hosting environment. */
+ #include <cfg/os.h>
+ #if OS_EMBEDDED
+ #define IRQ_DISABLE FIXME
+ #define IRQ_ENABLE FIXME
+ #define IRQ_SAVE_DISABLE(x) FIXME
+ #define IRQ_RESTORE(x) FIXME
+ typedef uint32_t cpuflags_t; // FIXME
+ #endif /* OS_EMBEDDED */
+
- #define CPU_REG_BITS 32
#define CPU_REGS_CNT 7
+ #define CPU_SAVED_REGS_CNT 7
#define CPU_STACK_GROWS_UPWARD 0
#define CPU_SP_ON_EMPTY_SLOT 0
#define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
#define CPU_HARVARD 0
+ #if CPU_X86_64
+ typedef uint64_t cpustack_t;
+ #define CPU_REG_BITS 64
+
+ #ifdef __WIN64__
+ /* WIN64 is an IL32-P64 weirdo. */
+ #define SIZEOF_LONG 4
+ #endif
+ #else
+ typedef uint32_t cpustack_t;
+ #define CPU_REG_BITS 32
+ #endif
+
+#elif CPU_ARM
+
+ #ifdef __IAR_SYSTEMS_ICC__
+
+ #include <inarm.h>
+
+ #define NOP __no_operation()
+ #define IRQ_DISABLE __disable_interrupt()
+ #define IRQ_ENABLE __enable_interrupt()
+
+ #define IRQ_SAVE_DISABLE(x) \
+ do { \
+ (x) = __get_CPSR(); \
+ __disable_interrupt(); \
+ } while (0)
+
+ #define IRQ_RESTORE(x) \
+ do { \
+ __set_CPSR(x); \
+ } while (0)
+
+ #define IRQ_GETSTATE() \
+ ((bool)(__get_CPSR() & 0xb0))
+
+ #else /* __IAR_SYSTEMS_ICC__ */
+
+ #warning "IRQ_ macros need testing!"
+
+ #define NOP asm volatile ("mov r0,r0" ::)
+
+ #define IRQ_DISABLE \
+ do { \
+ asm volatile ( \
+ "mrs r0, cpsr\n\t" \
+ "orr r0, r0, #0xb0\n\t" \
+ "msr cpsr, r0" \
+ :: \
+ ); \
+ } while (0)
+
+ #define IRQ_ENABLE \
+ do { \
+ asm volatile ( \
+ "mrs r0, cpsr\n\t" \
+ "bic r0, r0, #0xb0\n\t" \
+ "msr cpsr, r0" \
+ :: \
+ ); \
+ } while (0)
+
+ #define IRQ_SAVE_DISABLE(x) \
+ do { \
+ asm volatile ( \
+ "mrs r0, cpsr\n\t" \
+ "mov %0, r0\n\t" \
+ "orr r0, r0, #0xb0\n\t" \
+ "msr cpsr, r0" \
+ : "=r" (x) \
+ : /* no inputs */ \
+ : "r0" \
+ ); \
+ } while (0)
+
+ #define IRQ_RESTORE(x) \
+ do { \
+ asm volatile ( \
+ "mov r0, %0\n\t" \
+ "msr cpsr, r0" \
+ : /* no outputs */ \
+ : "r" (x) \
+ : "r0" \
+ ); \
+ } while (0)
+
+ #define IRQ_GETSTATE() \
+ ({ \
+ uint32_t sreg; \
+ asm volatile ( \
+ "mrs r0, cpsr\n\t" \
+ "mov %0, r0" \
+ : "=r" (sreg)
+ : /* no inputs */
+ : "r0" \
+ ); \
+ (bool)(sreg & 0xb0); \
+ })
+
+ #endif /* __IAR_SYSTEMS_ICC_ */
+
+ typedef uint32_t cpuflags_t;
+ typedef uint32_t cpustack_t;
+
+ /* Register counts include SREG too */
+ #define CPU_REG_BITS 32
+ #define CPU_REGS_CNT 16
+ #define CPU_SAVED_REGS_CNT FIXME
+ #define CPU_STACK_GROWS_UPWARD 0 //FIXME
+ #define CPU_SP_ON_EMPTY_SLOT 0 //FIXME
+ #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
+ #define CPU_HARVARD 0
+
#elif CPU_PPC
#define NOP asm volatile ("nop" ::)
+
#define IRQ_DISABLE FIXME
#define IRQ_ENABLE FIXME
#define IRQ_SAVE_DISABLE(x) FIXME
}
#define IRQ_GETSTATE() irq_getstate()
-
-
typedef uint16_t cpuflags_t;
typedef unsigned int cpustack_t;
*/
#define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
+#else
+ #error No CPU_... defined.
#endif
/*!
#else
#define CPU_PUSH_CALL_CONTEXT(sp, func) \
- CPU_PUSH_WORD((sp), (func))
+ CPU_PUSH_WORD((sp), (cpustack_t)(func))
#endif
#endif
#ifndef SIZEOF_PTR
-#define SIZEOF_PTR SIZEOF_INT
+#if CPU_REG_BITS < 32
+ #define SIZEOF_PTR 2
+#elif CPU_REG_BITS == 32
+ #define SIZEOF_PTR 4
+#else /* CPU_REG_BITS > 32 */
+ #define SIZEOF_PTR 8
+#endif
#endif
#ifndef CPU_BITS_PER_CHAR
STATIC_ASSERT(sizeof(short) == SIZEOF_SHORT);
STATIC_ASSERT(sizeof(long) == SIZEOF_LONG);
STATIC_ASSERT(sizeof(int) == SIZEOF_INT);
-
+STATIC_ASSERT(sizeof(void *) == SIZEOF_PTR);
+STATIC_ASSERT(sizeof(int8_t) * CPU_BITS_PER_CHAR == 8);
+STATIC_ASSERT(sizeof(uint8_t) * CPU_BITS_PER_CHAR == 8);
+STATIC_ASSERT(sizeof(int16_t) * CPU_BITS_PER_CHAR == 16);
+STATIC_ASSERT(sizeof(uint16_t) * CPU_BITS_PER_CHAR == 16);
+STATIC_ASSERT(sizeof(int32_t) * CPU_BITS_PER_CHAR == 32);
+STATIC_ASSERT(sizeof(uint32_t) * CPU_BITS_PER_CHAR == 32);
+#ifdef __HAS_INT64_T__
+STATIC_ASSERT(sizeof(int64_t) * CPU_BITS_PER_CHAR == 64);
+STATIC_ASSERT(sizeof(uint64_t) * CPU_BITS_PER_CHAR == 64);
+#endif
/*!
* \def CPU_IDLE
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