* \author Daniele Basile <asterix@develer.com>
*/
-#include <io/at91sam7s.h>
+#include <io/arm.h>
-//#include "ser_at91.h"
+#include <cpu/attr.h>
#include <drv/ser.h>
#include <drv/ser_p.h>
#include <hw/hw_ser.h> /* Required for bus macros overrides */
#include <hw/hw_cpu.h> /* CLOCK_FREQ */
-#include <appconfig.h>
#include <mware/fifobuf.h>
-
#include <cfg/debug.h>
-#include <drv/timer.h>
-
-
-//TODO
-#if !CONFIG_SER_HWHANDSHAKE
- /**
- * \name Hardware handshake (RTS/CTS).
- * \{
- */
- #define RTS_ON do {} while (0)
- #define RTS_OFF do {} while (0)
- #define IS_CTS_ON true
- #define EIMSKF_CTS 0 /**< Dummy value, must be overridden */
- /*\}*/
-#endif
-
-#if CPU_AVR_ATMEGA1281
- #define BIT_RXCIE0 RXCIE0
- #define BIT_RXEN0 RXEN0
- #define BIT_TXEN0 TXEN0
- #define BIT_UDRIE0 UDRIE0
- #define BIT_RXCIE1 RXCIE1
- #define BIT_RXEN1 RXEN1
- #define BIT_TXEN1 TXEN1
- #define BIT_UDRIE1 UDRIE1
-#else
- #define BIT_RXCIE0 RXCIE
- #define BIT_RXEN0 RXEN
- #define BIT_TXEN0 TXEN
- #define BIT_UDRIE0 UDRIE
-
- #define BIT_RXCIE1 RXCIE
- #define BIT_RXEN1 RXEN
- #define BIT_TXEN1 TXEN
- #define BIT_UDRIE1 UDRIE
-#endif
+#include <appconfig.h>
+#define SERIRQ_PRIORITY 4 ///< default priority for serial irqs.
/**
* \name Overridable serial bus hooks
*
* \{
*/
+
+#ifndef SER_UART0_IRQ_INIT
+ /**
+ * Default IRQ INIT macro - invoked in uart0_init()
+ *
+ * - Disable all interrupt
+ * - Register USART0 interrupt
+ * - Enable USART0 clock.
+ */
+ #define SER_UART0_IRQ_INIT do { \
+ US0_IDR = 0xFFFFFFFF; \
+ /* Set the vector. */ \
+ AIC_SVR(US0_ID) = uart0_irq_dispatcher; \
+ /* Initialize to edge triggered with defined priority. */ \
+ AIC_SMR(US0_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY; \
+ /* Enable the USART IRQ */ \
+ AIC_IECR = BV(US0_ID); \
+ PMC_PCER = BV(US0_ID); \
+ } while (0)
+#endif
+
#ifndef SER_UART0_BUS_TXINIT
/**
* Default TXINIT macro - invoked in uart0_init()
*
+ * - Disable GPIO on USART0 tx/rx pins
+ * - Reset USART0
+ * - Set serial param: mode Normal, 8bit data, 1bit stop
* - Enable both the receiver and the transmitter
* - Enable only the RX complete interrupt
*/
+ #if !CPU_ARM_AT91SAM7S256
+ #warning Check USART0 pins!
+ #endif
#define SER_UART0_BUS_TXINIT do { \
- UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \
+ PIOA_PDR = BV(RXD0) | BV(TXD0); \
+ US0_CR = BV(US_RSTRX) | BV(US_RSTTX); \
+ US0_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1; \
+ US0_CR = BV(US_RXEN) | BV(US_TXEN); \
+ US0_IER = BV(US_RXRDY); \
} while (0)
+
#endif
#ifndef SER_UART0_BUS_TXBEGIN
* Invoked before starting a transmission
*
* - Enable both the receiver and the transmitter
- * - Enable both the RX complete and UDR empty interrupts
+ * - Enable both the RX complete and TX empty interrupts
*/
#define SER_UART0_BUS_TXBEGIN do { \
- UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \
+ US0_CR = BV(US_RXEN) | BV(US_TXEN); \
+ US0_IER = BV(US_TXRDY) | BV(US_RXRDY); \
} while (0)
#endif
* Invoked to send one character.
*/
#define SER_UART0_BUS_TXCHAR(c) do { \
- UDR0 = (c); \
+ US0_THR = (c); \
} while (0)
#endif
*
* - Keep both the receiver and the transmitter enabled
* - Keep the RX complete interrupt enabled
- * - Disable the UDR empty interrupt
+ * - Disable the TX empty interrupts
*/
#define SER_UART0_BUS_TXEND do { \
- UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \
+ US0_CR = BV(US_RXEN) | BV(US_TXEN); \
+ US0_IER = BV(US_RXRDY); \
+ US0_IDR = BV(US_TXRDY); \
} while (0)
#endif
-#ifndef SER_UART0_BUS_TXOFF
- /**
- * \def SER_UART0_BUS_TXOFF
- *
- * Invoked after the last character has been transmitted
- *
- * The default is no action.
- */
- #ifdef __doxygen__
- #define SER_UART0_BUS_TXOFF
- #endif
+/* End USART0 macros */
+
+#ifndef SER_UART1_IRQ_INIT
+ /** \sa SER_UART0_BUS_TXINIT */
+ #define SER_UART1_IRQ_INIT do { \
+ US1_IDR = 0xFFFFFFFF; \
+ /* Set the vector. */ \
+ AIC_SVR(US1_ID) = uart1_irq_dispatcher; \
+ /* Initialize to edge triggered with defined priority. */ \
+ AIC_SMR(US1_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY; \
+ /* Enable the USART IRQ */ \
+ AIC_IECR = BV(US1_ID); \
+ PMC_PCER = BV(US1_ID); \
+ } while (0)
#endif
#ifndef SER_UART1_BUS_TXINIT
- /** \sa SER_UART0_BUS_TXINIT */
+ /** \sa SER_UART1_BUS_TXINIT */
+ #if !CPU_ARM_AT91SAM7S256
+ #warning Check USART1 pins!
+ #endif
#define SER_UART1_BUS_TXINIT do { \
- UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \
+ PIOA_PDR = BV(RXD1) | BV(TXD1); \
+ US1_CR = BV(US_RSTRX) | BV(US_RSTTX); \
+ US1_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1; \
+ US1_CR = BV(US_RXEN) | BV(US_TXEN); \
+ US1_IER = BV(US_RXRDY); \
} while (0)
#endif
+
#ifndef SER_UART1_BUS_TXBEGIN
- /** \sa SER_UART0_BUS_TXBEGIN */
+ /** \sa SER_UART1_BUS_TXBEGIN */
#define SER_UART1_BUS_TXBEGIN do { \
- UCSR1B = BV(BIT_RXCIE1) | BV(BIT_UDRIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \
+ US1_CR = BV(US_RXEN) | BV(US_TXEN); \
+ US1_IER = BV(US_TXRDY) | BV(US_RXRDY); \
} while (0)
#endif
+
#ifndef SER_UART1_BUS_TXCHAR
- /** \sa SER_UART0_BUS_TXCHAR */
+ /** \sa SER_UART1_BUS_TXCHAR */
#define SER_UART1_BUS_TXCHAR(c) do { \
- UDR1 = (c); \
+ US1_THR = (c); \
} while (0)
#endif
+
#ifndef SER_UART1_BUS_TXEND
- /** \sa SER_UART0_BUS_TXEND */
+ /** \sa SER_UART1_BUS_TXEND */
#define SER_UART1_BUS_TXEND do { \
- UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \
+ US1_CR = BV(US_RXEN) | BV(US_TXEN); \
+ US1_IER = BV(US_RXRDY); \
+ US1_IDR = BV(US_TXRDY); \
} while (0)
#endif
-#ifndef SER_UART1_BUS_TXOFF
- /**
- * \def SER_UART1_BUS_TXOFF
- *
- * \see SER_UART0_BUS_TXOFF
- */
- #ifdef __doxygen__
- #define SER_UART1_BUS_TXOFF
- #endif
-#endif
-/*\}*/
-
+#if 0
/**
* \name Overridable SPI hooks
*
#define SER_SPI_BUS_TXCLOSE
#endif
/*\}*/
-
-
-/* SPI port and pin configuration */
-#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103 || CPU_AVR_ATMEGA1281
- #define SPI_PORT PORTB
- #define SPI_DDR DDRB
- #define SPI_SS_BIT PB0
- #define SPI_SCK_BIT PB1
- #define SPI_MOSI_BIT PB2
- #define SPI_MISO_BIT PB3
-#elif CPU_AVR_ATMEGA8
- #define SPI_PORT PORTB
- #define SPI_DDR DDRB
- #define SPI_SS_BIT PB2
- #define SPI_SCK_BIT PB5
- #define SPI_MOSI_BIT PB3
- #define SPI_MISO_BIT PB4
-#else
- #error Unknown architecture
-#endif
-
-/* USART register definitions */
-#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281
- #define AVR_HAS_UART1 1
-#elif CPU_AVR_ATMEGA8
- #define AVR_HAS_UART1 0
- #define UCSR0A UCSRA
- #define UCSR0B UCSRB
- #define UCSR0C UCSRC
- #define UDR0 UDR
- #define UBRR0L UBRRL
- #define UBRR0H UBRRH
- #define SIG_UART0_DATA SIG_UART_DATA
- #define SIG_UART0_RECV SIG_UART_RECV
- #define SIG_UART0_TRANS SIG_UART_TRANS
-#elif CPU_AVR_ATMEGA103
- #define AVR_HAS_UART1 0
- #define UCSR0B UCR
- #define UDR0 UDR
- #define UCSR0A USR
- #define UBRR0L UBRR
- #define SIG_UART0_DATA SIG_UART_DATA
- #define SIG_UART0_RECV SIG_UART_RECV
- #define SIG_UART0_TRANS SIG_UART_TRANS
-#else
- #error Unknown architecture
#endif
-
/**
* \def CONFIG_SER_STROBE
*
/* TX and RX buffers */
static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
-#if AVR_HAS_UART1
- static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
- static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
-#endif
+
+static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
+static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
+
+#if 0
static unsigned char spi_txbuffer[CONFIG_SPI_TXBUFSIZE];
static unsigned char spi_rxbuffer[CONFIG_SPI_RXBUFSIZE];
-
+#endif
/**
* Internal hardware state structure
* is done by spi_starttx()). We do this *only* if a transfer is
* not already started.
*/
-struct AvrSerial
+struct ArmSerial
{
struct SerialHardware hw;
volatile bool sending;
* (and hopefully faster) code.
*/
struct Serial *ser_uart0 = &ser_handles[SER_UART0];
-#if AVR_HAS_UART1
struct Serial *ser_uart1 = &ser_handles[SER_UART1];
-#endif
-struct Serial *ser_spi = &ser_handles[SER_SPI];
-
+#if 0
+struct Serial *ser_spi = &ser_handles[SER_SPI];
+#endif
+static void uart0_irq_dispatcher(void);
+static void uart1_irq_dispatcher(void);
/*
- * Callbacks
+ * Callbacks for USART0
*/
static void uart0_init(
UNUSED_ARG(struct SerialHardware *, _hw),
UNUSED_ARG(struct Serial *, ser))
{
+ SER_UART0_IRQ_INIT;
SER_UART0_BUS_TXINIT;
- RTS_ON;
SER_STROBE_INIT;
}
static void uart0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
{
- UCSR0B = 0;
+ US0_CR = BV(US_RSTRX) | BV(US_RSTTX) | BV(US_RXDIS) | BV(US_TXDIS) | BV(US_RSTSTA);
}
static void uart0_enabletxirq(struct SerialHardware *_hw)
{
- struct AvrSerial *hw = (struct AvrSerial *)_hw;
+ struct ArmSerial *hw = (struct ArmSerial *)_hw;
/*
* WARNING: racy code here! The tx interrupt sets hw->sending to false
static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
{
/* Compute baud-rate period */
- uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
-
-#if !CPU_AVR_ATMEGA103
- UBRR0H = (period) >> 8;
-#endif
- UBRR0L = (period);
-
+ US0_BRGR = CLOCK_FREQ / (16 * rate);
//DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
}
static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
{
-#if !CPU_AVR_ATMEGA103
- UCSR0C = (UCSR0C & ~(BV(UPM01) | BV(UPM00))) | ((parity) << UPM00);
-#endif
-}
-
-#if AVR_HAS_UART1
+ US0_MR &= ~US_PAR_MASK;
+ /* Set UART parity */
+ switch(parity)
+ {
+ case SER_PARITY_NONE:
+ {
+ /* Parity mode. */
+ US0_MR |= US_PAR_NO;
+ break;
+ }
+ case SER_PARITY_EVEN:
+ {
+ /* Even parity.*/
+ US0_MR |= US_PAR_EVEN;
+ break;
+ }
+ case SER_PARITY_ODD:
+ {
+ /* Odd parity.*/
+ US0_MR |= US_PAR_ODD;
+ break;
+ }
+ default:
+ ASSERT(0);
+ }
+}
+/*
+ * Callbacks for USART1
+ */
static void uart1_init(
UNUSED_ARG(struct SerialHardware *, _hw),
UNUSED_ARG(struct Serial *, ser))
{
+ SER_UART1_IRQ_INIT;
SER_UART1_BUS_TXINIT;
- RTS_ON;
SER_STROBE_INIT;
}
static void uart1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
{
- UCSR1B = 0;
+ US1_CR = BV(US_RSTRX) | BV(US_RSTTX) | BV(US_RXDIS) | BV(US_TXDIS) | BV(US_RSTSTA);
}
static void uart1_enabletxirq(struct SerialHardware *_hw)
{
- struct AvrSerial *hw = (struct AvrSerial *)_hw;
+ struct ArmSerial *hw = (struct ArmSerial *)_hw;
/*
- * WARNING: racy code here! The tx interrupt
- * sets hw->sending to false when it runs with
- * an empty fifo. The order of the statements
- * in the if-block matters.
+ * WARNING: racy code here! The tx interrupt sets hw->sending to false
+ * when it runs with an empty fifo. The order of statements in the
+ * if-block matters.
*/
if (!hw->sending)
{
static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
{
/* Compute baud-rate period */
- uint16_t period = (((CLOCK_FREQ / 16UL) + (rate / 2)) / rate) - 1;
-
- UBRR1H = (period) >> 8;
- UBRR1L = (period);
-
- //DB(kprintf("uart1_setbaudrate(rate=%ld): period=%d\n", rate, period);)
+ US1_BRGR = CLOCK_FREQ / (16 * rate);
+ //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
}
static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
{
- UCSR1C = (UCSR1C & ~(BV(UPM11) | BV(UPM10))) | ((parity) << UPM10);
-}
+ US1_MR &= ~US_PAR_MASK;
+ /* Set UART parity */
+ switch(parity)
+ {
+ case SER_PARITY_NONE:
+ {
+ /* Parity mode. */
+ US1_MR |= US_PAR_NO;
+ break;
+ }
+ case SER_PARITY_EVEN:
+ {
+ /* Even parity.*/
+ US1_MR |= US_PAR_EVEN;
+ break;
+ }
+ case SER_PARITY_ODD:
+ {
+ /* Odd parity.*/
+ US1_MR |= US_PAR_ODD;
+ break;
+ }
+ default:
+ ASSERT(0);
+ }
-#endif // AVR_HAS_UART1
+}
+/* SPI driver */
+#if 0
static void spi_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
{
/*
{
// nop
}
+#endif
+
static bool tx_sending(struct SerialHardware* _hw)
{
- struct AvrSerial *hw = (struct AvrSerial *)_hw;
+ struct ArmSerial *hw = (struct ArmSerial *)_hw;
return hw->sending;
}
-
-
// FIXME: move into compiler.h? Ditch?
#if COMPILER_C99
#define C99INIT(name,val) .name = val
C99INIT(txSending, tx_sending),
};
-#if AVR_HAS_UART1
static const struct SerialHardwareVT UART1_VT =
{
C99INIT(init, uart1_init),
C99INIT(txStart, uart1_enabletxirq),
C99INIT(txSending, tx_sending),
};
-#endif // AVR_HAS_UART1
+#if 0
static const struct SerialHardwareVT SPI_VT =
{
C99INIT(init, spi_init),
C99INIT(txStart, spi_starttx),
C99INIT(txSending, tx_sending),
};
+#endif
-static struct AvrSerial UARTDescs[SER_CNT] =
+static struct ArmSerial UARTDescs[SER_CNT] =
{
{
C99INIT(hw, /**/) {
},
C99INIT(sending, false),
},
-#if AVR_HAS_UART1
{
C99INIT(hw, /**/) {
C99INIT(table, &UART1_VT),
},
C99INIT(sending, false),
},
-#endif
+#if 0
{
C99INIT(hw, /**/) {
C99INIT(table, &SPI_VT),
},
C99INIT(sending, false),
}
+#endif
};
struct SerialHardware *ser_hw_getdesc(int unit)
return &UARTDescs[unit].hw;
}
-
-/*
- * Interrupt handlers
- */
-
-#if CONFIG_SER_HWHANDSHAKE
-
-/// This interrupt is triggered when the CTS line goes high
-SIGNAL(SIG_CTS)
-{
- // Re-enable UDR empty interrupt and TX, then disable CTS interrupt
- UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
- EIMSK &= ~EIMSKF_CTS;
-}
-
-#endif // CONFIG_SER_HWHANDSHAKE
-
-
/**
* Serial 0 TX interrupt handler
*/
-SIGNAL(USART0_UDRE_vect)
+static void uart0_irq_tx(void)
{
SER_STROBE_ON;
if (fifo_isempty(txfifo))
{
SER_UART0_BUS_TXEND;
-#ifndef SER_UART0_BUS_TXOFF
UARTDescs[SER_UART0].sending = false;
-#endif
- }
-#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
- else if (!IS_CTS_ON)
- {
- // Disable rx interrupt and tx, enable CTS interrupt
- // UNTESTED
- UCSR0B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
- EIFR |= EIMSKF_CTS;
- EIMSK |= EIMSKF_CTS;
}
-#endif
else
{
char c = fifo_pop(txfifo);
SER_STROBE_OFF;
}
-#ifdef SER_UART0_BUS_TXOFF
/**
- * Serial port 0 TX complete interrupt handler.
- *
- * This IRQ is usually disabled. The UDR-empty interrupt
- * enables it when there's no more data to transmit.
- * We need to wait until the last character has been
- * transmitted before switching the 485 transceiver to
- * receive mode.
- *
- * The txfifo might have been refilled by putchar() while
- * we were waiting for the transmission complete interrupt.
- * In this case, we must restart the UDR empty interrupt,
- * otherwise we'd stop the serial port with some data
- * still pending in the buffer.
+ * Serial 0 RX complete interrupt handler.
*/
-SIGNAL(SIG_UART0_TRANS)
+static void uart0_irq_rx(void)
{
SER_STROBE_ON;
- struct FIFOBuffer * const txfifo = &ser_uart0->txfifo;
- if (fifo_isempty(txfifo))
- {
- SER_UART0_BUS_TXOFF;
- UARTDescs[SER_UART0].sending = false;
- }
+ /* Should be read before US_CRS */
+ ser_uart0->status |= US0_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
+
+ char c = US0_RHR;
+ struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo;
+
+ if (fifo_isfull(rxfifo))
+ ser_uart0->status |= SERRF_RXFIFOOVERRUN;
else
- UCSR0B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
+ fifo_push(rxfifo, c);
SER_STROBE_OFF;
}
-#endif /* SER_UART0_BUS_TXOFF */
-
-
-#if AVR_HAS_UART1
/**
- * Serial 1 TX interrupt handler
+ * Serial IRQ dispatcher for USART0.
*/
-SIGNAL(USART1_UDRE_vect)
+static void uart0_irq_dispatcher(void) __attribute__ ((naked));
+static void uart0_irq_dispatcher(void)
{
- SER_STROBE_ON;
+ IRQ_ENTRY();
- struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
+ if (US0_IMR & BV(US_RXRDY))
+ uart0_irq_rx();
- if (fifo_isempty(txfifo))
- {
- SER_UART1_BUS_TXEND;
-#ifndef SER_UART1_BUS_TXOFF
- UARTDescs[SER_UART1].sending = false;
-#endif
- }
-#if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
- else if (!IS_CTS_ON)
- {
- // Disable rx interrupt and tx, enable CTS interrupt
- // UNTESTED
- UCSR1B = BV(RXCIE) | BV(RXEN) | BV(TXEN);
- EIFR |= EIMSKF_CTS;
- EIMSK |= EIMSKF_CTS;
- }
-#endif
- else
- {
- char c = fifo_pop(txfifo);
- SER_UART1_BUS_TXCHAR(c);
- }
+ if (US0_IMR & BV(US_TXRDY))
+ uart0_irq_tx();
- SER_STROBE_OFF;
+ IRQ_EXIT();
}
-#ifdef SER_UART1_BUS_TXOFF
/**
- * Serial port 1 TX complete interrupt handler.
- *
- * \sa port 0 TX complete handler.
+ * Serial 1 TX interrupt handler
*/
-SIGNAL(SIG_UART1_TRANS)
+static void uart1_irq_tx(void)
{
SER_STROBE_ON;
struct FIFOBuffer * const txfifo = &ser_uart1->txfifo;
+
if (fifo_isempty(txfifo))
{
- SER_UART1_BUS_TXOFF;
+ SER_UART1_BUS_TXEND;
UARTDescs[SER_UART1].sending = false;
}
- else
- UCSR1B = BV(RXCIE) | BV(UDRIE) | BV(RXEN) | BV(TXEN);
-
- SER_STROBE_OFF;
-}
-#endif /* SER_UART1_BUS_TXOFF */
-
-#endif // AVR_HAS_UART1
-
-
-/**
- * Serial 0 RX complete interrupt handler.
- *
- * This handler is interruptible.
- * Interrupt are reenabled as soon as recv complete interrupt is
- * disabled. Using INTERRUPT() is troublesome when the serial
- * is heavily loaded, because an interrupt could be retriggered
- * when executing the handler prologue before RXCIE is disabled.
- *
- * \note The code that re-enables interrupts is commented out
- * because in some nasty cases the interrupt is retriggered.
- * This is probably due to the RXC flag being set before
- * RXCIE is cleared. Unfortunately the RXC flag is read-only
- * and can't be cleared by code.
- */
-SIGNAL(USART0_RX_vect)
-{
- SER_STROBE_ON;
-
- /* Disable Recv complete IRQ */
- //UCSR0B &= ~BV(RXCIE);
- //IRQ_ENABLE;
-
- /* Should be read before UDR */
- ser_uart0->status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
-
- /* To clear the RXC flag we must _always_ read the UDR even when we're
- * not going to accept the incoming data, otherwise a new interrupt
- * will occur once the handler terminates.
- */
- char c = UDR0;
- struct FIFOBuffer * const rxfifo = &ser_uart0->rxfifo;
-
- if (fifo_isfull(rxfifo))
- ser_uart0->status |= SERRF_RXFIFOOVERRUN;
else
{
- fifo_push(rxfifo, c);
-#if CONFIG_SER_HWHANDSHAKE
- if (fifo_isfull(rxfifo))
- RTS_OFF;
-#endif
+ char c = fifo_pop(txfifo);
+ SER_UART1_BUS_TXCHAR(c);
}
- /* Reenable receive complete int */
- //IRQ_DISABLE;
- //UCSR0B |= BV(RXCIE);
-
SER_STROBE_OFF;
}
-
-#if AVR_HAS_UART1
-
/**
* Serial 1 RX complete interrupt handler.
- *
- * This handler is interruptible.
- * Interrupt are reenabled as soon as recv complete interrupt is
- * disabled. Using INTERRUPT() is troublesome when the serial
- * is heavily loaded, because an interrupt could be retriggered
- * when executing the handler prologue before RXCIE is disabled.
- *
- * \see SIGNAL(USART1_RX_vect)
*/
-SIGNAL(USART1_RX_vect)
+static void uart1_irq_rx(void)
{
SER_STROBE_ON;
- /* Disable Recv complete IRQ */
- //UCSR1B &= ~BV(RXCIE);
- //IRQ_ENABLE;
+ /* Should be read before US_CRS */
+ ser_uart1->status |= US1_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
- /* Should be read before UDR */
- ser_uart1->status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
-
- /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
- * not going to accept the incoming data
- */
- char c = UDR1;
+ char c = US1_RHR;
struct FIFOBuffer * const rxfifo = &ser_uart1->rxfifo;
- //ASSERT_VALID_FIFO(rxfifo);
- if (UNLIKELY(fifo_isfull(rxfifo)))
+ if (fifo_isfull(rxfifo))
ser_uart1->status |= SERRF_RXFIFOOVERRUN;
else
- {
fifo_push(rxfifo, c);
-#if CONFIG_SER_HWHANDSHAKE
- if (fifo_isfull(rxfifo))
- RTS_OFF;
-#endif
- }
- /* Re-enable receive complete int */
- //IRQ_DISABLE;
- //UCSR1B |= BV(RXCIE);
SER_STROBE_OFF;
}
-#endif // AVR_HAS_UART1
-
-
/**
- * SPI interrupt handler
+ * Serial IRQ dispatcher for USART1.
*/
-SIGNAL(SIG_SPI)
+static void uart1_irq_dispatcher(void) __attribute__ ((naked));
+static void uart1_irq_dispatcher(void)
{
- SER_STROBE_ON;
+ IRQ_ENTRY();
- /* Read incoming byte. */
- if (!fifo_isfull(&ser_spi->rxfifo))
- fifo_push(&ser_spi->rxfifo, SPDR);
- /*
- * FIXME
- else
- ser_spi->status |= SERRF_RXFIFOOVERRUN;
- */
+ if (US1_IMR & BV(US_RXRDY))
+ uart1_irq_rx();
- /* Send */
- if (!fifo_isempty(&ser_spi->txfifo))
- SPDR = fifo_pop(&ser_spi->txfifo);
- else
- UARTDescs[SER_SPI].sending = false;
+ if (US1_IMR & BV(US_TXRDY))
+ uart1_irq_tx();
- SER_STROBE_OFF;
+ IRQ_EXIT();
}
projects / bertos.git / blobdiff