* For additional information see http://www.ethernut.de/
*/
-#ifndef _AT91_US_H_
-#define _AT91_US_H_
+#ifndef AT91_US_H
+#define AT91_US_H
/**
* USART Control Register
*/
/*\{*/
#define US_CR_OFF 0x00000000 ///< USART control register offset.
-#define US0_CR (*((reg32_t *)(USART0_BASE + US_CR_OFF) ///< Channel 0 control register address.
-#define US1_CR (*((reg32_t *)(USART1_BASE + US_CR_OFF) ///< Channel 1 control register address.
-#define US_RSTRX 2 ///< Reset receiver. */
+#define US0_CR (*((reg32_t *)(USART0_BASE + US_CR_OFF))) ///< Channel 0 control register address.
+#define US1_CR (*((reg32_t *)(USART1_BASE + US_CR_OFF))) ///< Channel 1 control register address.
+#define US_RSTRX 2 ///< Reset receiver.
#define US_RSTTX 3 ///< Reset transmitter.
#define US_RXEN 4 ///< Receiver enable.
#define US_RXDIS 5 ///< Receiver disable.
#define US_STTTO 11 ///< Start timeout.
#define US_SENDA 12 ///< Send next byte with address bit set.
#define US_RSTIT 13 ///< Reset interations.
-#define US_RTSNAK 14 ///< Reset non acknowledge.
+#define US_RSTNAK 14 ///< Reset non acknowledge.
#define US_RETTO 15 ///< Rearm time out.
#define US_DTREN 16 ///< Data terminal ready enable.
#define US_DTRDIS 17 ///< Data terminal ready disable.
*/
/*\{*/
#define US_MR_OFF 0x00000004 ///< USART mode register offset.
-#define US0_MR (*((reg32_t *)(USART0_BASE + US_MR_OFF) ///< Channel 0 mode register address.
-#define US1_MR (*((reg32_t *)(USART1_BASE + US_MR_OFF) ///< Channel 1 mode register address.
+#define US0_MR (*((reg32_t *)(USART0_BASE + US_MR_OFF))) ///< Channel 0 mode register address.
+#define US1_MR (*((reg32_t *)(USART1_BASE + US_MR_OFF))) ///< Channel 1 mode register address.
#define US_USART_MODE_MASK 0x0000000F ///< USART mode mask.
#define US_USART_MODE_NORMA 0x00000000 ///< Normal.
#define US_USART_MODE_MODEM 0x00000003 ///< Modem.
#define US_USART_MODE_ISO7816T0 0x00000004 ///< ISO7816 protocol: T=0.
#define US_USART_MODE_ISO7816T1 0x00000006 ///< ISO7816 protocol: T=1.
-#define US_USART_MODE_RS485 0x00000008 ///< IrDA.
+#define US_USART_MODE_IRDA 0x00000008 ///< IrDA.
#define US_CLKS_MASK 0x00000030 ///< Clock selection mask.
#define US_CLKS_MCK 0x00000000 ///< Master clock.
*/
/*\{*/
#define US_IER_OFF 0x00000008 ///< USART interrupt enable register offset.
-#define US0_IER (*((reg32_t *)(USART0_BASE + US_IER_OFF) ///< Channel 0 interrupt enable register address.
-#define US1_IER (*((reg32_t *)(USART1_BASE + US_IER_OFF) ///< Channel 1 interrupt enable register address.
+#define US0_IER (*((reg32_t *)(USART0_BASE + US_IER_OFF))) ///< Channel 0 interrupt enable register address.
+#define US1_IER (*((reg32_t *)(USART1_BASE + US_IER_OFF))) ///< Channel 1 interrupt enable register address.
#define US_IDR_OFF 0x0000000C ///< USART interrupt disable register offset.
-#define US0_IDR (*((reg32_t *)(USART0_BASE + US_IDR_OFF) ///< Channel 0 interrupt disable register address.
-#define US1_IDR (*((reg32_t *)(USART1_BASE + US_IDR_OFF) ///< Channel 1 interrupt disable register address.
+#define US0_IDR (*((reg32_t *)(USART0_BASE + US_IDR_OFF))) ///< Channel 0 interrupt disable register address.
+#define US1_IDR (*((reg32_t *)(USART1_BASE + US_IDR_OFF))) ///< Channel 1 interrupt disable register address.
#define US_IMR_OFF 0x00000010 ///< USART interrupt mask register offset.
-#define US0_IMR (*((reg32_t *)(USART0_BASE + US_IMR_OFF) ///< Channel 0 interrupt mask register address.
-#define US1_IMR (*((reg32_t *)(USART1_BASE + US_IMR_OFF) ///< Channel 1 interrupt mask register address.
+#define US0_IMR (*((reg32_t *)(USART0_BASE + US_IMR_OFF))) ///< Channel 0 interrupt mask register address.
+#define US1_IMR (*((reg32_t *)(USART1_BASE + US_IMR_OFF))) ///< Channel 1 interrupt mask register address.
#define US_CSR_OFF 0x00000014 ///< USART status register offset.
-#define US0_CSR (*((reg32_t *)(USART0_BASE + US_CSR_OFF) ///< Channel 0 status register address.
-#define US1_CSR (*((reg32_t *)(USART1_BASE + US_CSR_OFF) ///< Channel 1 status register address.
+#define US0_CSR (*((reg32_t *)(USART0_BASE + US_CSR_OFF))) ///< Channel 0 status register address.
+#define US1_CSR (*((reg32_t *)(USART1_BASE + US_CSR_OFF))) ///< Channel 1 status register address.
#define US_CSR_RI 20 ///< Image of RI input.
#define US_CSR_DSR 21 ///< Image of DSR input.
#define US_CSR_DCD 22 ///< Image of DCD input.
*/
/*\{*/
#define US_RHR_OFF 0x00000018 ///< USART receiver holding register offset.
-#define US0_RHR (*((reg32_t *)(USART0_BASE + US_RHR_OFF) ///< Channel 0 receiver holding register address.
-#define US1_RHR (*((reg32_t *)(USART1_BASE + US_RHR_OFF) ///< Channel 1 receiver holding register address.
+#define US0_RHR (*((reg32_t *)(USART0_BASE + US_RHR_OFF))) ///< Channel 0 receiver holding register address.
+#define US1_RHR (*((reg32_t *)(USART1_BASE + US_RHR_OFF))) ///< Channel 1 receiver holding register address.
#define US_RHR_RXCHR_MASK 0x000001FF ///< Last char received if US_RXRDY is set.
#define US_RHR_RXSYNH 15 ///< Received sync.
/*\}*/
*/
/*\{*/
#define US_THR_OFF 0x0000001C ///< USART transmitter holding register offset.
-#define US0_THR (*((reg32_t *)(USART0_BASE + US_THR_OFF) ///< Channel 0 transmitter holding register address.
-#define US1_THR (*((reg32_t *)(USART1_BASE + US_THR_OFF) ///< Channel 1 transmitter holding register address.
+#define US0_THR (*((reg32_t *)(USART0_BASE + US_THR_OFF))) ///< Channel 0 transmitter holding register address.
+#define US1_THR (*((reg32_t *)(USART1_BASE + US_THR_OFF))) ///< Channel 1 transmitter holding register address.
#define US_THR_TXCHR_MASK 0x000001FF ///< Next char to be trasmitted.
#define US_THR_TXSYNH 15 ///< Sync field to be trasmitted.
/*\}*/
*/
/*\{*/
#define US_BRGR_OFF 0x00000020 ///< USART baud rate register offset.
-#define US0_BRGR (*((reg32_t *)(USART0_BASE + US_BRGR_OFF) ///< Channel 0 baud rate register address.
-#define US1_BRGR (*((reg32_t *)(USART1_BASE + US_BRGR_OFF) ///< Channel 1 baud rate register address.
-#define US_BRGR_MASK 0x0000FFFF ///< Clock divider.
-#define US_BRGR_FP_MASK 0x001F0000 ///< Fractional part.
+#define US0_BRGR (*((reg32_t *)(USART0_BASE + US_BRGR_OFF))) ///< Channel 0 baud rate register address.
+#define US1_BRGR (*((reg32_t *)(USART1_BASE + US_BRGR_OFF))) ///< Channel 1 baud rate register address.
/*\}*/
/**
*/
/*\{*/
#define US_RTOR_OFF 0x00000024 ///< USART receiver timeout register offset.
-#define US0_RTOR (*((reg32_t *)(USART0_BASE + US_RTOR_OFF) ///< Channel 0 receiver timeout register address.
-#define US1_RTOR (*((reg32_t *)(USART1_BASE + US_RTOR_OFF) ///< Channel 1 receiver timeout register address.
+#define US0_RTOR (*((reg32_t *)(USART0_BASE + US_RTOR_OFF))) ///< Channel 0 receiver timeout register address.
+#define US1_RTOR (*((reg32_t *)(USART1_BASE + US_RTOR_OFF))) ///< Channel 1 receiver timeout register address.
/*\}*/
/**
*/
/*\{*/
#define US_TTGR_OFF 0x00000028 ///< USART transmitter time guard register offset.
-#define US0_TTGR (*((reg32_t *)(USART0_BASE + US_TTGR_OFF) ///< Channel 0 transmitter time guard register address.
-#define US1_TTGR (*((reg32_t *)(USART1_BASE + US_TTGR_OFF) ///< Channel 1 transmitter time guard register address.
+#define US0_TTGR (*((reg32_t *)(USART0_BASE + US_TTGR_OFF))) ///< Channel 0 transmitter time guard register address.
+#define US1_TTGR (*((reg32_t *)(USART1_BASE + US_TTGR_OFF))) ///< Channel 1 transmitter time guard register address.
/*\}*/
/**
*/
/*\{*/
#define US_FIDI_OFF 0x00000040 ///< USART FI DI ratio register offset.
-#define US0_FIDI (*((reg32_t *)(USART0_BASE + US_FIDI_OFF) ///< Channel 0 FI DI ratio register address.
-#define US1_FIDI (*((reg32_t *)(USART1_BASE + US_FIDI_OFF) ///< Channel 1 FI DI ratio register address.
+#define US0_FIDI (*((reg32_t *)(USART0_BASE + US_FIDI_OFF))) ///< Channel 0 FI DI ratio register address.
+#define US1_FIDI (*((reg32_t *)(USART1_BASE + US_FIDI_OFF))) ///< Channel 1 FI DI ratio register address.
/*\}*/
/**
*/
/*\{*/
#define US_NER_OFF 0x00000044 ///< USART error counter register offset.
-#define US0_NER (*((reg32_t *)(USART0_BASE + US_NER_OFF) ///< Channel 0 error counter register address.
-#define US1_NER (*((reg32_t *)(USART1_BASE + US_NER_OFF) ///< Channel 1 error counter register address.
+#define US0_NER (*((reg32_t *)(USART0_BASE + US_NER_OFF))) ///< Channel 0 error counter register address.
+#define US1_NER (*((reg32_t *)(USART1_BASE + US_NER_OFF))) ///< Channel 1 error counter register address.
/*\}*/
/**
*/
/*\{*/
#define US_IF_OFF 0x0000004C ///< USART IrDA filter register offset.
-#define US0_IF (*((reg32_t *)(USART0_BASE + US_IF_OFF) ///< Channel 0 IrDA filter register address.
-#define US1_IF (*((reg32_t *)(USART1_BASE + US_IF_OFF) ///< Channel 1 IrDA filter register address.
+#define US0_IF (*((reg32_t *)(USART0_BASE + US_IF_OFF))) ///< Channel 0 IrDA filter register address.
+#define US1_IF (*((reg32_t *)(USART1_BASE + US_IF_OFF))) ///< Channel 1 IrDA filter register address.
/*\}*/
-#if defined(*((reg32_t *)(USART_HAS_PDC)
+#if USART_HAS_PDC
+
+ /**
+ * Receive Pointer Register
+ */
+ /*\{*/
+ #define US0_RPR (*((reg32_t *)(USART0_BASE + PERIPH_RPR_OFF))) ///< Channel 0 receive pointer register address.
+ #define US1_RPR (*((reg32_t *)(USART1_BASE + PERIPH_RPR_OFF))) ///< Channel 1 receive pointer register address.
+ /*\}*/
+
+ /**
+ * Receive Counter Register
+ */
+ /*\{*/
+ #define US0_RCR (*((reg32_t *)(USART0_BASE + PERIPH_RCR_OFF))) ///< Channel 0 receive counter register address.
+ #define US1_RCR (*((reg32_t *)(USART1_BASE + PERIPH_RCR_OFF))) ///< Channel 1 receive counter register address.
+ /*\}*/
+
+ /**
+ * Transmit Pointer Register
+ */
+ /*\{*/
+ #define US0_TPR (*((reg32_t *)(USART0_BASE + PERIPH_TPR_OFF))) ///< Channel 0 transmit pointer register address.
+ #define US1_TPR (*((reg32_t *)(USART1_BASE + PERIPH_TPR_OFF))) ///< Channel 1 transmit pointer register address.
+ /*\}*/
+
+ /**
+ * Transmit Counter Register
+ */
+ /*\{*/
+ #define US0_TCR (*((reg32_t *)(USART0_BASE + PERIPH_TCR_OFF))) ///< Channel 0 transmit counter register address.
+ #define US1_TCR (*((reg32_t *)(USART1_BASE + PERIPH_TCR_OFF))) ///< Channel 1 transmit counter register address.
+ /*\}*/
+
+ #if defined(PERIPH_RNPR_OFF) && defined(PERIPH_RNCR_OFF)
+ #define US0_RNPR (*((reg32_t *)(USART0_BASE + PERIPH_RNPR_OFF))) ///< PDC channel 0 receive next pointer register.
+ #define US1_RNPR (*((reg32_t *)(USART1_BASE + PERIPH_RNPR_OFF))) ///< PDC channel 1 receive next pointer register.
+ #define US0_RNCR (*((reg32_t *)(USART0_BASE + PERIPH_RNCR_OFF))) ///< PDC channel 0 receive next counter register.
+ #define US1_RNCR (*((reg32_t *)(USART1_BASE + PERIPH_RNCR_OFF))) ///< PDC channel 1 receive next counter register.
+ #endif
+
+ #if defined(PERIPH_TNPR_OFF) && defined(PERIPH_TNCR_OFF)
+ #define US0_TNPR (*((reg32_t *)(USART0_BASE + PERIPH_TNPR_OFF))) ///< PDC channel 0 transmit next pointer register.
+ #define US1_TNPR (*((reg32_t *)(USART1_BASE + PERIPH_TNPR_OFF))) ///< PDC channel 1 transmit next pointer register.
+ #define US0_TNCR (*((reg32_t *)(USART0_BASE + PERIPH_TNCR_OFF))) ///< PDC channel 0 transmit next counter register.
+ #define US1_TNCR (*((reg32_t *)(USART1_BASE + PERIPH_TNCR_OFF))) ///< PDC channel 1 transmit next counter register.
+ #endif
+
+ #if defined(PERIPH_PTCR_OFF)
+ #define US0_PTCR (*((reg32_t *)(USART0_BASE + PERIPH_PTCR_OFF))) ///< PDC channel 0 transfer control register.
+ #define US1_PTCR (*((reg32_t *)(USART1_BASE + PERIPH_PTCR_OFF))) ///< PDC channel 1 transfer control register.
+ #endif
+
+ #if defined(PERIPH_PTSR_OFF)
+ #define US0_PTSR (*((reg32_t *)(USART0_BASE + PERIPH_PTSR_OFF))) ///< PDC channel 0 transfer status register.
+ #define US1_PTSR (*((reg32_t *)(USART1_BASE + PERIPH_PTSR_OFF))) ///< PDC channel 1 transfer status register.
+ #endif
+
+#endif /* USART_HAS_PDC */
+
/**
- * Receive Pointer Register
+ * SPI Control Register
+ * \{
*/
-/*\{*/
-#define US0_RPR (*((reg32_t *)(USART0_BASE + PERIPH_RPR_OFF) ///< Channel 0 receive pointer register address.
-#define US1_RPR (*((reg32_t *)(USART1_BASE + PERIPH_RPR_OFF) ///< Channel 1 receive pointer register address.
+#define SPI_CR_OFF 0x00000000 ///< Control register offset.
+#define SPI_CR (*((reg32_t *)(SPI_BASE + SPI_CR_OFF))) ///< SPI control register.
+#define SPI_SPIEN 0 ///< SPI enable.
+#define SPI_SPIDIS 1 ///< SPI disable.
+#define SPI_SWRST 7 ///< Software reset.
+#define SPI_LASTXFER 24 ///< Last transfer.
/*\}*/
/**
- * Receive Counter Register
+ * SPI Mode Register
+ * \{
*/
-/*\{*/
-#define US0_RCR (*((reg32_t *)(USART0_BASE + PERIPH_RCR_OFF) ///< Channel 0 receive counter register address.
-#define US1_RCR (*((reg32_t *)(USART1_BASE + PERIPH_RCR_OFF) ///< Channel 1 receive counter register address.
+#define SPI_MR_OFF 0x00000004 ///< Mode register offset.
+#define SPI_MR (*((reg32_t *)(SPI_BASE + SPI_MR_OFF))) ///< SPI mode register.
+#define SPI_MSTR 0 ///< Master mode.
+#define SPI_PS 1 ///< Peripheral select.
+#define SPI_PCSDEC 2 ///< Chip select decode.
+#define SPI_MODFDIS 4 ///< Mode fault detection.
+#define SPI_LLB 7 ///< Local loopback enable.
+#define SPI_PCS 0x000F0000 ///< Peripheral chip select mask.
+#define SPI_PCS_0 0x000E0000 ///< Peripheral chip select 0.
+#define SPI_PCS_1 0x000D0000 ///< Peripheral chip select 1.
+#define SPI_PCS_2 0x000B0000 ///< Peripheral chip select 2.
+#define SPI_PCS_3 0x00070000 ///< Peripheral chip select 3.
+#define SPI_PCS_LSB 16 ///< Least significant bit of peripheral chip select.
+#define SPI_DLYBCS 0xFF000000 ///< Mask for delay between chip selects.
+#define SPI_DLYBCS_LSB 24 ///< Least significant bit of delay between chip selects.
/*\}*/
/**
- * Transmit Pointer Register
+ * SPI Receive Data Register
+ * \{
*/
-/*\{*/
-#define US0_TPR (*((reg32_t *)(USART0_BASE + PERIPH_TPR_OFF) ///< Channel 0 transmit pointer register address.
-#define US1_TPR (*((reg32_t *)(USART1_BASE + PERIPH_TPR_OFF) ///< Channel 1 transmit pointer register address.
+#define SPI_RDR_OFF 0x00000008 ///< Receive data register offset.
+#define SPI_RDR (*((reg32_t *)(SPI_BASE + SPI_RDR_OFF))) ///< SPI receive data register.
+#define SPI_RD 0x0000FFFF ///< Receive data mask.
+#define SPI_RD_LSB 0 ///< Least significant bit of receive data.
/*\}*/
/**
- * Name Transmit Counter Register
+ * SPI Transmit Data Register
+ * \{
*/
-/*\{*/
-#define US0_TCR (*((reg32_t *)(USART0_BASE + PERIPH_TCR_OFF) ///< Channel 0 transmit counter register address.
-#define US1_TCR (*((reg32_t *)(USART1_BASE + PERIPH_TCR_OFF) ///< Channel 1 transmit counter register address.
+#define SPI_TDR_OFF 0x0000000C ///< Transmit data register offset.
+#define SPI_TDR (*((reg32_t *)(SPI_BASE + SPI_TDR_OFF))) ///< SPI transmit data register.
+#define SPI_TD 0x0000FFFF ///< Transmit data mask.
+#define SPI_TD_LSB 0 ///< Least significant bit of transmit data.
/*\}*/
-#if defined(PERIPH_RNPR_OFF) && defined(PERIPH_RNCR_OFF)
-#define US0_RNPR (*((reg32_t *)(USART0_BASE + PERIPH_RNPR_OFF) ///< PDC channel 0 receive next pointer register.
-#define US1_RNPR (*((reg32_t *)(USART1_BASE + PERIPH_RNPR_OFF) ///< PDC channel 1 receive next pointer register.
-#define US0_RNCR (*((reg32_t *)(USART0_BASE + PERIPH_RNCR_OFF) ///< PDC channel 0 receive next counter register.
-#define US1_RNCR (*((reg32_t *)(USART1_BASE + PERIPH_RNCR_OFF) ///< PDC channel 1 receive next counter register.
-#endif
-
-#if defined(PERIPH_TNPR_OFF) && defined(PERIPH_TNCR_OFF)
-#define US0_TNPR (*((reg32_t *)(USART0_BASE + PERIPH_TNPR_OFF) ///< PDC channel 0 transmit next pointer register.
-#define US1_TNPR (*((reg32_t *)(USART1_BASE + PERIPH_TNPR_OFF) ///< PDC channel 1 transmit next pointer register.
-#define US0_TNCR (*((reg32_t *)(USART0_BASE + PERIPH_TNCR_OFF) ///< PDC channel 0 transmit next counter register.
-#define US1_TNCR (*((reg32_t *)(USART1_BASE + PERIPH_TNCR_OFF) ///< PDC channel 1 transmit next counter register.
-#endif
-
-#if defined(PERIPH_PTCR_OFF)
-#define US0_PTCR (*((reg32_t *)(USART0_BASE + PERIPH_PTCR_OFF) ///< PDC channel 0 transfer control register.
-#define US1_PTCR (*((reg32_t *)(USART1_BASE + PERIPH_PTCR_OFF) ///< PDC channel 1 transfer control register.
-#endif
-
-#if defined(PERIPH_PTSR_OFF)
-#define US0_PTSR (*((reg32_t *)(USART0_BASE + PERIPH_PTSR_OFF) ///< PDC channel 0 transfer status register.
-#define US1_PTSR (*((reg32_t *)(USART1_BASE + PERIPH_PTSR_OFF) ///< PDC channel 1 transfer status register.
-#endif
-
-#endif /* USART_HAS_PDC */
-
+/**
+ * SPI Status and Interrupt Register
+ * \{
+ */
+#define SPI_SR_OFF 0x00000010 ///< Status register offset.
+#define SPI_SR (*((reg32_t *)(SPI_BASE + SPI_SR_OFF))) ///< Status register.
+#define SPI_IER_OFF 0x00000014 ///< Interrupt enable register offset.
+#define SPI_IER (*((reg32_t *)(SPI_BASE + SPI_IER_OFF))) ///< Interrupt enable register.
+#define SPI_IDR_OFF 0x00000018 ///< Interrupt disable register offset.
+#define SPI_IDR (*((reg32_t *)(SPI_BASE + SPI_IDR_OFF))) ///< Interrupt disable register.
+#define SPI_IMR_OFF 0x0000001C ///< Interrupt mask register offset.
+#define SPI_IMR (*((reg32_t *)(SPI_BASE + SPI_IMR_OFF))) ///< Interrupt mask register.
+
+#define SPI_RDRF 0 ///< Receive data register full.
+#define SPI_TDRE 1 ///< Transmit data register empty.
+#define SPI_MODF 2 ///< Mode fault error.
+#define SPI_OVRES 3 ///< Overrun error status.
+#define SPI_ENDRX 4 ///< End of RX buffer.
+#define SPI_ENDTX 5 ///< End of TX buffer.
+#define SPI_RXBUFF 6 ///< RX buffer full.
+#define SPI_TXBUFE 7 ///< TX buffer empty.
+#define SPI_NSSR 8 ///< NSS rising.
+#define SPI_TXEMPTY 9 ///< Transmission register empty.
+#define SPI_SPIENS 16 ///< SPI enable status.
+/*\}*/
-#endif /* _AT91_US_H_ */
+/**
+ * SPI Chip Select Registers
+ * \{
+ */
+#define SPI_CSR0_OFF 0x00000030 ///< Chip select register 0 offset.
+#define SPI_CS0 (*((reg32_t *)(SPI_BASE + SPI_CSR0_OFF))) ///< Chip select register 0.
+#define SPI_CSR1_OFF 0x00000034 ///< Chip select register 1 offset.
+#define SPI_CS1 (*((reg32_t *)(SPI_BASE + SPI_CSR1_OFF))) ///< Chip select register 1.
+#define SPI_CSR2_OFF 0x00000038 ///< Chip select register 2 offset.
+#define SPI_CS2 (*((reg32_t *)(SPI_BASE + SPI_CSR2_OFF))) ///< Chip select register 2.
+#define SPI_CSR3_OFF 0x0000003C ///< Chip select register 3 offset.
+#define SPI_CS3 (*((reg32_t *)(SPI_BASE + SPI_CSR3_OFF))) ///< Chip select register 3.
+
+#define SPI_CPOL 0 ///< Clock polarity.
+#define SPI_NCPHA 1 ///< Clock phase.
+#define SPI_CSAAT 3 ///< Chip select active after transfer.
+#define SPI_BITS 0x000000F0 ///< Bits per transfer mask.
+#define SPI_BITS_8 0x00000000 ///< 8 bits per transfer.
+#define SPI_BITS_9 0x00000010 ///< 9 bits per transfer.
+#define SPI_BITS_10 0x00000020 ///< 10 bits per transfer.
+#define SPI_BITS_11 0x00000030 ///< 11 bits per transfer.
+#define SPI_BITS_12 0x00000040 ///< 12 bits per transfer.
+#define SPI_BITS_13 0x00000050 ///< 13 bits per transfer.
+#define SPI_BITS_14 0x00000060 ///< 14 bits per transfer.
+#define SPI_BITS_15 0x00000070 ///< 15 bits per transfer.
+#define SPI_BITS_16 0x00000080 ///< 16 bits per transfer.
+#define SPI_BITS_LSB 4 ///< Least significant bit of bits per transfer.
+#define SPI_SCBR 0x0000FF00 ///< Serial clock baud rate mask.
+#define SPI_SCBR_LSB 8 ///< Least significant bit of serial clock baud rate.
+#define SPI_DLYBS 0x00FF0000 ///< Delay before SPCK mask.
+#define SPI_DLYBS_LSB 16 ///< Least significant bit of delay before SPCK.
+#define SPI_DLYBCT 0xFF000000 ///< Delay between consecutive transfers mask.
+#define SPI_DLYBCT_LSB 24 ///< Least significant bit of delay between consecutive transfers.
+/*\}*/
+#endif /* AT91_US_H */
projects / bertos.git / blobdiff