Move AT91 SPI register definitions.

[bertos.git] / cpu / arm / io / at91sam7.h

diff --git a/cpu/arm/io/at91sam7.h b/cpu/arm/io/at91sam7.h
index f91690e82fa05b3c7c1673353dfe981b89f36024..a3f5ab14f314623bf54bbf9b36fb4b05089b5281 100644 (file)
--- a/cpu/arm/io/at91sam7.h
+++ b/cpu/arm/io/at91sam7.h
@@ -76,7 +76,7 @@
 
 #include <cfg/compiler.h>
 
-#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7S256
+#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128 || CPU_ARM_AT91SAM7S256
        #define FLASH_BASE      0x100000UL
        #define RAM_BASE        0x200000UL
 
@@ -100,7 +100,7 @@
        #define VREG_BASE       0xFFFFFD60      ///< Voltage regulator mode controller base address.
        #define MC_BASE         0xFFFFFF00      ///< Memory controller base.
 
-       #if CPU_ARM_AT91SAM7X256
+       #if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
                #define CAN_BASE        0xFFFD0000      ///< PWM controller base address.
                #define EMAC_BASE       0xFFFDC000      ///< Ethernet MAC address.
                #define SPI0_BASE       0xFFFE0000      ///< SPI0 base address.
@@ -136,13 +136,17 @@
 #include "at91_pio.h"
 #include "at91_us.h"
 #include "at91_dbgu.h"
+#include "at91_tc.h"
+#include "at91_pwm.h"
+#include "at91_spi.h"
+#include "at91_twi.h"
 //TODO: add other peripherals
 
 /**
  * Peripheral Identifiers and Interrupts
  *\{
  */
-#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7S256
+#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7S256 || CPU_ARM_AT91SAM7X128
        #define FIQ_ID      0       ///< Fast interrupt ID.
        #define SYSC_ID     1       ///< System controller interrupt.
        #define US0_ID      6       ///< USART 0 ID.
@@ -158,7 +162,7 @@
        #define IRQ0_ID     30      ///< External interrupt 0 ID.
        #define IRQ1_ID     31      ///< External interrupt 1 ID.
 
-       #if CPU_ARM_AT91SAM7X256
+       #if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
                #define PIOA_ID     2       ///< Parallel A I/O controller ID.
                #define PIOB_ID     3       ///< Parallel B I/O controller ID.
                #define SPI0_ID     4       ///< Serial peripheral interface 0 ID.
@@ -175,7 +179,7 @@
                /* ID 3 is reserved */
                #define ADC_ID      4       ///< Analog to digital converter ID.
                #define SPI_ID      5       ///< Serial peripheral interface ID.
-
+               #define SPI0_ID     SPI_ID  ///< Alias
        #endif
 
 #else
@@ -185,7 +189,7 @@
 /*\}*/
 
 /**
- * USART pins name
+ * USART & DEBUG pin names
  *\{
  */
 #if CPU_ARM_AT91SAM7S256
@@ -193,16 +197,17 @@
        #define TXD0        6
        #define RXD1       21
        #define TXD1       22
-
-#elif CPU_ARM_AT91SAM7X256
-       #define RXD0       0 // PA0
-       #define TXD0       1 // PA1
-       #define RXD1       5 // PA5
-       #define TXD1       6 // PA6
-
+       #define DTXD       10
+       #define DRXD        9
+#elif CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
+       #define RXD0        0 // PA0
+       #define TXD0        1 // PA1
+       #define RXD1        5 // PA5
+       #define TXD1        6 // PA6
+       #define DTXD       28 // PA28
+       #define DRXD       27 // PA27
 #else
-       #error No USART pins name definition for selected ARM CPU
-
+       #error No USART & debug pin names definition for selected ARM CPU
 #endif
 /*\}*/
 
@@ -211,12 +216,12 @@
  *\{
  */
 #if CPU_ARM_AT91SAM7S256
-       #define NPCS0      11  // Same as NSS pin.
-       #define MISO       12
-       #define MOSI       13
-       #define SPCK       14
+       #define SPI0_NPCS0      11  // Same as NSS pin.
+       #define SPI0_MISO       12
+       #define SPI0_MOSI       13
+       #define SPI0_SPCK       14
 
-#elif CPU_ARM_AT91SAM7X256
+#elif CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
        #define SPI0_NPCS0  12 // Same as NSS pin. PA12
        #define SPI0_NPCS1  13 // PA13
        #define SPI0_NPCS2  14 // PA14
@@ -239,4 +244,51 @@
 #endif
 /*\}*/
 
+/**
+ * Timer counter pins definition.
+ *\{
+ */
+#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
+       #define TIOA0  23 // PB23
+       #define TIOB0  24 // PB24
+       #define TIOA1  25 // PB25
+       #define TIOB1  26 // PB26
+       #define TIOA2  27 // PB27
+       #define TIOB2  28 // PB28
+
+#else
+       #error No Timer Conter pin names definition for selected ARM CPU
+
+#endif
+/*\}*/
+
+/**
+ * PWM pins definition.
+ *\{
+ */
+#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
+       #define TIOA0  23 // PB23
+       #define TIOB0  24 // PB24
+       #define TIOA1  25 // PB25
+       #define TIOB1  26 // PB26
+       #define TIOA2  27 // PB27
+       #define TIOB2  28 // PB28
+
+#else
+       #error No Timer Conter pin names definition for selected ARM CPU
+
+#endif
+/*\}*/
+
+/**
+ * TWI pins definition.
+ *\{
+ */
+#if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
+       #define TWD  10
+       #define TWCK 11
+#else
+       #error No TWI pin names definition for selected ARM CPU
+#endif
+
 #endif /* AT91SAM7_H */