Rename CPU_MEMORY_BARRIER to MEMORY_BARRIER and move it in compiler header.

[bertos.git] / cpu / attr.h

diff --git a/cpu/attr.h b/cpu/attr.h
index 497f899700d2712816480bd0792a53c4fd177dd9..ce6e4ae38d35823c5b083860b97ff1c2ad5cf66a 100644 (file)
--- a/cpu/attr.h
+++ b/cpu/attr.h
@@ -45,6 +45,7 @@
 #include <cfg/compiler.h> /* for uintXX_t */
 #include <cfg/arch_config.h>  /* ARCH_EMUL */
 
+#include "appconfig.h" // CONFIG_FAST_MEM
 
 /**
  * \name Macros for determining CPU endianness.
@@ -102,13 +103,25 @@
        #define CPU_SAVED_REGS_CNT     9
        #define CPU_STACK_GROWS_UPWARD 0
        #define CPU_SP_ON_EMPTY_SLOT   0
-       #define CPU_BYTE_ORDER         (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
        #define CPU_HARVARD            0
 
        #ifdef __IAR_SYSTEMS_ICC__
-               #define NOP         __no_operation()
-       #else /* !__IAR_SYSTEMS_ICC__ */
-               #define NOP         asm volatile ("mov r0,r0" ::)
+               #warning Check CPU_BYTE_ORDER
+               #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
+
+               #define NOP            __no_operation()
+
+       #else /* GCC and compatibles */
+
+               #if defined(__ARMEB__)
+                       #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
+               #elif defined(__ARMEL__)
+                       #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
+               #else
+                       #error Unable to detect ARM endianness!
+               #endif
+
+               #define NOP            asm volatile ("mov r0,r0" ::)
 
                /**
                 * Initialization value for registers in stack frame.
@@ -124,6 +137,34 @@
                 */
                #define CPU_REG_INIT_VALUE(reg) (reg == (CPU_SAVED_REGS_CNT - 1) ? 0x13 : 0)
 
+               #if CONFIG_FAST_MEM
+                       /**
+                        * Function attribute for use with performance critical code.
+                        *
+                        * On the AT91 family, code residing in flash has wait states.
+                        * Moving functions to the data section is a quick & dirty way
+                        * to get them transparently copied to SRAM for zero-wait-state
+                        * operation.
+                        */
+                       #define FAST_FUNC __attribute__((section(".data")))
+
+                       /**
+                        * Data attribute to move constant data to fast memory storage.
+                        *
+                        * \see FAST_FUNC
+                        */
+                       #define FAST_RODATA __attribute__((section(".data")))
+
+               #else // !CONFIG_FAST_MEM
+                       #define FAST_RODATA /**/
+                       #define FAST_FUNC /**/
+               #endif
+
+               /**
+                * Function attribute to declare an interrupt service routine.
+                */
+               #define ISR_FUNC __attribute__((interrupt))
+
        #endif /* !__IAR_SYSTEMS_ICC_ */
 
 #elif CPU_PPC
@@ -257,8 +298,8 @@
                } while (0)
 
        /*
-        * If the kernel is in idle-spinning, the processor execute:
-        * 
+        * If the kernel is in idle-spinning, the processor executes:
+        *
         * IRQ_ENABLE;
         * CPU_IDLE;
         * IRQ_DISABLE;